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參數(shù)資料
| 型號： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 76/128頁 |
| 文件大小： | 752K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
MOTOROLA
6-7
TIMERS
6
OCF - Output Compare Flag
1 (set)
–
A valid output compare has occurred on Output Compare register.
0 (clear) –
No output compare has occurred on Output Compare register.
OCF will be set when the Output Compare register contents match that of the free-running
counter; an output compare interrupt will be generated, if OCIE is set. OCF is cleared by reading
the TSR and then the Output Compare Low register ($17).
TOF - Timer Overow Flag
1 (set)
–
Timer Overow has occurred.
0 (clear) –
No timer overow has occurred.
This bit is set when the free-running counter overows from $FFFF to $0000; a timer overow
interrupt will occur, if TOIE (bit 5 in Timer Control register $12) is set. TOF is cleared by reading
the TSR and the counter low register ($19).
When using the timer overow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overow ag is unintentionally
cleared if:
1) the timer status register is read or written when the TOF is set, and
2) the LSB of the free-running counter is read, but not for the purpose of
servicing the ag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
6.1.6
Programmable Timer Timing Diagrams
The relationships between the internal clock signals, the counter contents and the status of the
ag bits are shown in the following diagrams. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and Reset) are not available to the user.
TPG
49
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