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參數(shù)資料
| 型號： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 114/128頁 |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC05BS8FB |
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MOTOROLA
9-10
MC68HC05BS8
SYNC SIGNAL PROCESSOR
9
9.10.4
Interrupt Line Count Register (ILCR)
This is a read/write register containing the line number for which the Vertical Sync Interrupt is to
be generated. Interrupt will be generated if VSIE bit is set, I bit in CCR is cleared, and the internal
line counter value matches the setting in this register after the Vsync pulse. The Vsync Interrupt
Vectors are at $3FF8 and $3FF9, and the interrupt latch is cleared by fetching the interrupt
vectors.
VSIE - Vsync Interrupt Enable
This bit enables and disables the Vsync interrupt.
1 (set)
–
Vsync interrupt enabled.
0 (clear) –
Vsync interrupt disabled.
LC6:0 - Line Count for Vsync Interrupt
These 7 bits store the line number for which the Vsync Interrupt will occur. The number is ranged
from 0 to 127.
9.10.5
Sampling Pulse Register (SPR)
This read/write register contains the line number for which the sampling pulse in SAM output to
be generated. The line number is ranged from 0 to 127. Sampling pulses are produced when there
is a Vsync pulse, or this register matches the horizontal line counter.
9.11
System Operation
The sync processor accepts sync signals from the main computer; the signals can either be
separate Hsync and Vsync or composite sync through HSYNC input. Polarity correction is
performed before the sync signals go any further into the system. The sync pulse detection blocks
will continuously monitor the signal, to see if it is active. If the signal is not active, the circuit will
switch to output the internally generated clock signal. This will protect the circuits behind from
being damaged by an inactive signal.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
ILCR
$000E
VSIE
LC6
LC5
LC4
LC3
LC2
LC1
LC0
0000 0010
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
SPR
$000F
SP6
SP5
SP4
SP3
SP2
SP1
SP0
0000 0010
TPG
84
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