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參數(shù)資料
| 型號(hào)： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 108/128頁(yè) |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC05BS8FB |
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MOTOROLA
9-4
MC68HC05BS8
SYNC SIGNAL PROCESSOR
9
9.5
Sync Separation
Figure 9-2 is a block diagram of the Sync Separator which includes the duration counters for the
high and low pulses, a counter for the number of valid horizontal sync pulses, a register to hold
the number of horizontal lines per frame, a logic block for horizontal and vertical sync pulse
separation, a comparator, and a sync pulse insertion circuit.
The Low pulse duration counter examines the low pulse width of the incoming composite sync
signal. If it is within the horizontal sync pulse limit (8
s or 16 t
CYC), a horizontal sync pulse is
detected, and the horizontal line counter is advanced. If the low pulse is wider than the limit, a
vertical sync pulse is detected, and the content of the Horizontal line counter is loaded into the
Horizontal Line register. The Low pulse duration counter then resets the Horizontal line counter.
The High Pulse Duration Counter examines the high pulse width of the incoming composite sync
signal. If it is longer than a specic value (8
s or 16 t
CYC), the vertical sync pulse has nished and
a “nish” signal will be given to the Sync Separation Logic.
Sync Separation Logic passes the Csync signal to the Hsync output until there is an “equal” signal
from the comparator. The Hsync output will then output an reassembled waveform by the Sync
Insertion Circuit to emulate the Hsync pulses, and the Vsync output is set to “l(fā)ow” at the coming
falling edge of the Csync signal. After the “nish” signal has been sensed, the Vsync output is xed
to “high”, and the Hsync output follows the Csync input again.
Figure 9-2 Sync Separator
Sync separation logic
Sync insertion circuit
Comparator
Low pulse duration counter
High pulse duration counter
Horizontal Line Register
Horizontal Line counter
CLK
Csync
load
reset
count
in
out
equal
Hsync
Vsync
nish
Csync
Vertical
TPG
78
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