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參數(shù)資料
| 型號： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 71/128頁 |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
MOTOROLA
6-3
TIMERS
6
6.1.1
Counter
–
Counter Register location
High byte - $18, Low byte - $19
–
Alternate Counter Register
High byte - $1A, Low byte - $1B
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 0.95
s if the internal bus clock is 4.2MHz. The counter is incremented during
the low portion of the internal bus clock. Software can read the counter at any time without
affecting its value.
The double-byte, free-running counter can be read from either of two locations, $18 and $19
(counter register) or $1A and $1B (counter alternate register). Reading only the least signicant
byte (LSB) of the free-running counter ($19 or $1B) receives the count value at the time of the
read. If the most signicant byte (MSB) ($18 or $1A) is read rst, the LSB ($19 or $1B) is
transferred to a buffer. This buffer value remains xed after the rst MSB read, even if the MSB is
read several times. This buffer is accessed when the LSB ($19 or $1B) is read, and thus,
completes a read sequence of the complete counter value.
Reading the Timer Counter register low byte after reading the timer Status Register clears the
timer overow ag (TOF), but reading the Counter Alternate register does not affect TOF.
Therefore, the counter alternate register can be read any time without risk of missing timer
overow interrupts due to a cleared TOF.
The free-running counter is preset to $FFFC during reset and is always a read-only register.
During a power-on reset, the counter is also preset to $FFFC and begins running after the
oscillator start-up delay. The value in the free-running counter repeats every 262144 internal bus
clock cycles. TOF is set when the counter overows (from $FFFF to $0000); this will cause an
interrupt if TOIE (bit 5 of TCR) is set.
In some timing control applications it may be desirable to reset the counter under software control.
When the low byte of the counter ($19 or $1B) is written to, the counter is set to its reset value of
$FFFC. The divide-by-4 prescaler is also reset and the counter resumes normal counting
operation. All of the ags and enable bits remain unaltered by this operation. If access has
previously been made to the high byte of the free-running counter ($18 or $1A), then the reset
counter operation terminates the access sequence.
TPG
45
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