參數(shù)資料
型號: MC68HC05BS8FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 66/128頁
文件大?。?/td> 752K
代理商: MC68HC05BS8FB
MOTOROLA
5-8
MC68HC05BS8
RESETS AND INTERRUPTS
5
2) A match of the calling address with its own specic address in slave mode -
MAAS set.
3) A loss of bus arbitration - MAL set.
This bit must be cleared by software in the interrupt routine.
MCF - Data Transfer Complete
1 (set)
A byte transfer has been completed.
0 (clear) –
A byte is being transfer.
MAAS - Addressed as Slave
1 (set)
Currently addressed as a slave.
0 (clear) –
Not currently addressed.
Then CPU needs to check the SRW bit and set its MTX bit accordingly. Writing to the M-Bus
Control register clears this bit.
MAL - Arbitration Lost
1 (set)
Lost arbitration in master mode.
0 (clear) –
No arbitration lost.
SIF - Software M-Bus Interrupt
1 (set)
Signals on PC6 and PC7 pins satisfy the “start” condition for the “soft”
M-Bus protocol. This bit cannot be set if the SIIC bit in the MCR is
cleared. An interrupt to the CPU is generated only if the I-bit in the
CCR is also cleared.
0 (clear) –
No “soft” M-Bus interrupt.
Refer to Section 8 for detailed description of M-Bus Interface.
5.2.2.4
Timer Interrupts
There are three interrupt sources from the 16-bit free-running counter timer.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer Status Register
$0013
ICF
OCF
TOF
uuu0 0000
TPG
40
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