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參數(shù)資料
| 型號： | M44C510D-XXX-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 封裝： | SSOP-44 |
| 文件頁數(shù)： | 9/60頁 |
| 文件大?。?/td> | 709K |
| 代理商： | M44C510D-XXX-DOW |
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M44C510E
Preliminary Information
Rev. A1, 04-May-00
17 (60)
1.5.5
Clock Monitor Mode
13387
SYSCL clocks
NRST
TE
BP11
Oscillator supervisory mode
Normal operation
BP10
SUBCL clocks
Figure 16. Clock monitoring
For trimming purposes, the M44C510E can be put into a
clock monitor mode. By forcing the test input (TE) high,
the SYSCL clock will appear on BP11 (Port 1, bit 1) and
SUBCL clock on Port BP10 (Port 1, bit 0). On releasing
the TE pin, the BP10 and BP11 will resume their normal
function (see figure 16).
2
Peripheral Modules
2.1
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O
bus (see figure 17). The IN or OUT instructions allow
direct addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted which addresses the
“primary register” directly. To address the “auxiliary reg-
ister”, the access must be switched with an “auxiliary
switching module”. Thus, a single IN (or OUT) to the
module address will read (or write) into the module pri-
mary register. Accessing the auxiliary register is
performed with the same instruction preceded by writing
the module address into the auxiliary switching module.
Byte-wide registers are accessed by multiple IN (or OUT)
instructions. Extended addressing is used for more com-
plex peripheral modules, with a larger number of
registers. In this case, a bank of up to 16 subport registers
are indirectly addressed with the subport address being
initially written into the auxiliary register. Please refer to
the ’HARDC510.SCR’ hardware interface file as a pro-
gramming guideline.
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