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| 型號(hào)： | M44C510D-XXX-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 封裝： | SSOP-44 |
| 文件頁數(shù)： | 5/60頁 |
| 文件大?。?/td> | 709K |
| 代理商： | M44C510D-XXX-DOW |
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M44C510E
Preliminary Information
Rev. A1, 04-May-00
13 (60)
1.5
Clock Generation
1.5.1
Clock Module
The clock module generates two clocks. The system
clock (SYSCL) supplies the CPU and the peripherals
while the lower frequency periphery sub-clock (SUBCL)
supplies only the peripherals. The modes for clock
sources are programmable with the OS1-bit and OS0-bit
in the SC-register and the CCS-bit in the CM-register.
The clock module includes 4 different internal oscillator
types: two RC-oscillators, one 4-MHz crystal oscillator
and one 32-kHz crystal oscillator. The pins OSC1 and
OSC2 provide the interface to connect a crystal either for
the 4-MHz, or the 32-kHz crystal oscillator. SCLIN can
be used as an input for an external clock or for connecting
an external trimming resistor for the RC-oscillator 2. All
necessary components with the exception of the crystal
and the trimming resistor are integrated on-chip. Any one
of these clock sources can be selected to generate the
system clock (SYSCL).
In applications that do not require exact timing, it is
possible to use the fully integrated RC-oscillator 1
without any external components. The RC-oscillator 2 is
more stable but the oscillator frequency must be trimmed
with an external resistor attached between SCLIN and
VDD. In this configuration, for system clock frequencies
below 2 MHz,the RC-oscillator 2 frequency can be
maintained to within a tolerance of
± 10% over the full
operating temperature and voltage range.
The clock module is programmable via software using the
clock management register (CM) and the system
configuration register (SC). The required oscillator
configuration is selected with the OS[1:0]-bits in the
SC-register. A programmable 4-bit divider stage allows
the
adjustment
of
the
system
clock
speed.
A
synchronization stage avoids any clock glitches which
could be caused by clock source switching.
The CPU always requires SYSCL clocks to execute
instructions, process interrupts and enter or leave the
SLEEP state. Internal oscillators are, depending on the
condition of the NSTOP-bit automatically stopped and
started where necessary. Special care must however be
taken when using an external clock source which is gated
by a one of the microcontroller port signals. This configu-
ration can hang up if the external oscillator is switched off
while the external clock source is still selected. It is there-
fore advisable in such a case to switch first to the internal
RC-oscillator 1 source using CSS-bit. The external source
can then be reselected later when the external oscillator
has again been restarted.
Ext. clock
ExIn
ExOut
Stop
RC oscillator2
RCOut2
Stop
R
Trim
4–MHz oscillator
4Out
Stop
Oscin
Oscout
32–kHz oscillator
32Out
Oscin
Oscout
RC
oscillator 1
RCOut1
Control
Stop
IN1
IN2
/2
Divider chain
Sleep
Stop
NSTOP
CCS
CSS1
CSS0
CM:
OS1
OS0
SUBCL
SYSCL
SC:
*
OSCIN
*
OSCOUT
*
mask option
32 kHz
13386
SCLIN
SYSCLmax
/8
SYSCLmax/64
RC[1:0]
SC:
to CPU
and
Timer/
counter
Figure 10. Clock module
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