參數(shù)資料
型號： M44C510D-XXX-DOW
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER
封裝： SSOP-44
文件頁數(shù)： 36/60頁
文件大?。?/td> 709K
代理商： M44C510D-XXX-DOW
M44C510E
Preliminary Information
Rev. A1, 04-May-00
41 (60)
Period Measurement Modes (Rising and Falling Edge)
During the period measurement mode, the counter counts the number of either internal or external clocks in one period
of the BP41 input signal (see figure 36). Dependent on the mode chosen, this will be from rising edge to the next rising
edge or conversely, falling edge to the following falling edge. On the trigger edge, the counter state is loaded into the
capture register and subsequently reset. The measured value remains in the capture register until overwritten by the
following measured value. Interrupts can be generated by either an overflow condition or an end-of-measurement
(eom) event. An ’eom’ event signals the CPU that a new measured value is present in the capture register and can be
read, if required.
T0IN1
(BP41)
t_period
”eom”
Interrupt
Captures and resets timer
Falling edge triggered
t_period
Rising edge triggered
96 11542
Figure 36. Period measurement
Pulse Width Measurement Modes (High and Low)
In this mode, the selected clock source is gated to the counter for the duration of each input pulse received on BP41
(see figure 37). Whether the measurement takes place during the high or low phase depends on the selected mode. At
the end of each pulse, the counter state is loaded into the capture register and subsequently reset. Interrupts can be gen-
erated by either an overflow condition or an end-of-measurement (eom) event. An ’eom’ event signals the CPU that
a new measured value is present in the capture register can be read, if required.
T0IN1
(BP41)
t_low
t_high
”eom”
Interrupt
Captures and resets timer
96 11543
Figure 37. Pulse width measurement
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