參數(shù)資料
型號(hào)： M44C510D-XXX-DOW
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER
封裝： SSOP-44
文件頁(yè)數(shù)： 7/60頁(yè)
文件大?。?/td> 709K
代理商： M44C510D-XXX-DOW
M44C510E
Preliminary Information
Rev. A1, 04-May-00
15 (60)
4-MHz Oscillator
The integrated system clock oscillator requires an exter-
nal crystal or ceramic resonator connected between the
OSCIN and OSCOUT pins to establish oscillation. All the
necessary oscillator circuitry, with the exception of the
actual crystal, resonator and the optional C3 and C4 are
integrated on-chip.
4–MHz
oscillator
4Out
Stop
4Out
Osc–Stop
13379
OSCIN
OSCOUT
*
Oscin
C1
*
C2
Oscout
Cer.
Res
*
mask option
C3
C4
XTAL
Figure 14. System clock oscillator
32-kHz Oscillator
Some applications require accurate long-term time
keeping without putting excessive demands on the CPU
or alternatively low resolution computing power. In this
case, the on-chip ultra low power 32-kHz crystal
oscillator can be used to generate both the SUBCL and/or
the SYSCL. In this mode, power consumption can be sig-
nificantly reduced. The 32-kHz crystal oscillator will
remain operating (not stopped) during any CPU power-
down/SLEEP mode.
32–kHz
oscillator
32Out
13380
OSCIN
OSCOUT
*
Oscin
C1
*
C2
Oscout
XTAL
32 kHz
*
mask option
Figure 15. 32-kHz crystal oscillator
1.5.3
Clock Management Register (CM)
The clock management register (CM) controls the system clock divider chain, as well as the peripheral clock in the
power-down modes.
Auxiliary register address: ’E’hex
Bit 3
Bit 2
Bit 1
Bit 0
CM:
NSTOP
CCS
CSS1
CSS0
Reset value: 1111b
NSTOP
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock (SUBCL) when the core is in SLEEP mode.
The 32-kHz crystal oscillator SUBCL clock cannot be stopped.
NSTOP = 1, enables the peripheral clock (SUBCL) when the core in SLEEP mode
CCS
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the
RC-oscillator 2 (with the external resistor) will generate SYSCL dependent on the setting of
OS0 and OS1 in the system configuration register
CSS[1:0]
Core Speed Select
These two bits control the system clock divider chain
Auxiliary register address: ’E’hex
CSS1
CSS0
Divider
Note
0
0
16
SYSCLmax/8
0
1
8
SYSCLmax/4
1
0
4
SYSCLmax/2
1
1
2
Reset value = SYSCLmax
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