
M44C510E
Preliminary Information
Rev. A1, 04-May-00
5 (60)
1
MARC4 Architecture
Instruction
decoder
CCR
TOS
ALU
RAM
PC
RP
SP
X
Y
Program
256 x 4-bit
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
Reset
System
clock
Interrupt
controller
On–chip peripheral modules
94 8973
memory
Figure 3. MARC4 core
1.1
General Description
The MARC4 microcontroller consists of an advanced
stack based 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with physi-
cally separate program memory (ROM) and data memory
(RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus are used for parallel commu-
nication between ROM, RAM and peripherals. This
enhances program execution speed by allowing both
instruction prefetching, and a simultaneous communica-
tion to the on-chip peripheral circuitry. The extremely
powerful integrated interrupt controller with associated
eight prioritized interrupt levels supports fast and effi-
cient processing of hardware events. The MARC4 is
designed for the high-level programming language
qFORTH. The core includes an expression and a return
stack. This architecture allows high-level language pro-
gramming without any loss in efficiency or code density.
1.2
Components of MARC4 Core
The core contains ROM, RAM, ALU, a program counter,
RAM address registers, an instruction decoder and an
interrupt controller. The following sections describe each
functional block in more detail:
1.2.1
ROM
The program memory (ROM) is mask programmed with
the customer application program during the fabrication
of the microcontroller. The ROM is addressed by a 12-bit
wide program counter, thus predefining a maximum pro-
gram bank size of 4 Kbytes. An additional 1 Kbyte of
ROM exists which is used partly for a quality control self-
test program. The remaining space is available for the
application program. The access to this additional ROM
section is done by using a ROM-bank switch.