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參數(shù)資料
| 型號： | M44C510D-XXX-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 封裝： | SSOP-44 |
| 文件頁數(shù)： | 20/60頁 |
| 文件大?。?/td> | 709K |
| 代理商： | M44C510D-XXX-DOW |
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M44C510E
Preliminary Information
Rev. A1, 04-May-00
27 (60)
2.2.6
TIM1 – Dedicated Timer 1 I/O Pin
T1IN (Timer 1 input)
T1OUT (Timer 1 output)
T1Dir (direction control)
V
DD
VDD
TIM1
Mask options
*
Pull-up
Pull-down
*
96 11528
Figure 24. Bidirectional pin TIM1
TIM1 is a dedicated bidirectional I/O stage for signal
communication to and from the Timer 1 in the timer/
counter module (see figure 24). It has no I/O bus interface
and is not directly accessible from the CPU. The direction
control is performed from the timer/counter configura-
tion registers.
2.3
Interval Timers / Prescaler
The interval timers are based on a frequency divider for
generating two independent time base interrupts. It is
driven by SUBCL generated by the clock module (see fig-
ure 10 ) and consists of a 15-stage binary divider and two
programmable multiplexers for selecting the appropriate
interrupt frequencies for each interrupt source (see fig-
ure 25). Each multiplexer is completely independent and
is controlled by the common Interval Timer Frequency
Select Register (ITFSR). Buffer registers store the respec-
tive frequency select codes and ensure complete
programming independence of each interrupt channel.
Interrupt masking and programming of the interrupt
priority levels is performed with the aid of the Interval
Timer Interrupt Priority Register (ITIPR).
SUBCL
CK
8092Hz
4096Hz
2048Hz
1024Hz
256Hz
128Hz
64Hz
32Hz
8Hz
4Hz
2Hz
1Hz
0h
1h
2h
3h
4h
5h
6h
7h
2Hz
4Hz
8Hz
16Hz
32Hz
64Hz
128Hz
8Hz
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
16Hz
64Hz
256Hz
1024Hz
2048Hz
4096Hz
8192Hz
ITFSR
FS1
FS2
FS3
FS0
Buffer
ITIPR
MIA
PRA
PRB
MIB
INTA
8:1
Mux
INTB
8:1
Mux
INT5
INT1
INT6
INT2
R
15-stage binary counter
2
22
2
22
2
22
2
22
2
34
5
6
7
8
9
10
11
12
13
14
15
(e.g. SUBCL = 32 kHz)
96 11530
Figure 25. Interval timers / prescaler
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