參數(shù)資料
型號: M44C510D-XXX-DOW
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER
封裝: SSOP-44
文件頁數(shù): 40/60頁
文件大小: 709K
代理商: M44C510D-XXX-DOW
M44C510E
Preliminary Information
Rev. A1, 04-May-00
45 (60)
Timer 1 Counter Free Running (50% Duty Cycle)
In the free running counter mode, the counter counts up with either an internal or external clock and cycles through
all 256 timer states. On the clock following a match between the compare register (T1CR) and the counter, a compare
interrupt (if unmasked) is generated and the TIM1 pin is toggled (see figure 40).
Timer
Clock
T1OUT
(TIM1)
Compare
Interrupt
Timer = compare register (= 4)
04
255
Timer
State
1
2
35 6
4
1
2
35 6
0
255
4
1
2
35 6
0
(clock set to rising edge)
50% duty
cycle
96 11546
Figure 40. Timer 1 counter free running (50% duty cycle)
Timer 1 Counter Auto Reload (Strobe and 50% Duty Cycle)
In the auto-reload mode, the counter counts up with either an internal or external clock. On the clock cycle following
a match between the compare register (T1CR) and the counter, a compare interrupt (if unmasked) is generated. The
TIM1 output is either strobed or toggled and the counter reset (see figure 41). Therefore, the counter cycle period is
defined by the contents of the compare register. In 50% duty cycle mode the frequency of TIM1 is:
fTIM1 = fin/2(n+1)
where the compare value (n) =1 ... 255.
Timer
Clock
T1OUT
(TIM1)
Compare
Interrupt
Timer = compare register (= 7)
Resets timer
0
7
Timer
State
0
50% duty
cycle
strobe
4
1
2
35 6
7 0
4
1
2
35 6
7 0
4
1
2
35 6
(clock set to neg. edge)
96 11547
Figure 41. Timer 1 counter auto reload
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