參數(shù)資料
型號(hào)： M44C510D-XXX-DOW
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER
封裝： SSOP-44
文件頁(yè)數(shù)： 35/60頁(yè)
文件大小： 709K
代理商： M44C510D-XXX-DOW
M44C510E
Rev. A1, 04-May-00
Preliminary Information
40 (60)
Timer 0 Pulse Width Modulation Mode
A pulse width modulated (PWM) signal exhibits a fixed repetition frequency and a variable mark space ratio. It is often
used as a simple method for D/A conversion, where the high period is proportional to the digital value to be converted.
Therefore by connecting a simple low-pass RC network to the PWM signal, the analog value can be retrieved.
Timer 0 generates the PWM signal by comparing the state of the free running up counter with the contents of the
compare register (see figure 34). If the result is less than the compare register value, then the BP41 output is high. If
the result is greater or equal to the compare register value, then the BP41 output is set low. Thus, the high phase of
the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space
ratios can be generated ranging from a continuous low signal over a variable pulse width signal to a continuous high
signal. The PWM signal has a repetition period of 256 clocks, an interrupt (if unmasked) being generated on every
overflow event. Care should be taken if the SYSCL clock is used as the PWM clock source because it may stop if the
CPU goes into SLEEP mode (see Section 1.5.4 Power-Down Modes).
Timer
Clock
T0OUT1
(BP41)
Overflow
Interrupt
Timer = compare register (= 4)
04
255
Timer
State
t_hi
t_low
t_hi = (comparator value)*clock period
t_low = (255–comparator value)*clock period
1
2
3
255
04
1
3
255
04
1
3
96 11540
Figure 34. Timer 0 pulse width modulation
Pulse Density Modulation Mode
Pulse density modulation (PDM) is also used for simple D/A conversion. Unlike the PWM signal,where the high and
low signal phases are always continuous during a single repetition cycle, the PDM distributes these evenly as a series
of pulses (see figure 35). This has the advantage that, if used together with an RC smoothing filter for D/A conversion,
either the ripple is less than the PWM, or, for a corresponding ripple error, the filter components can be smaller or the
clock frequency lower. To generate the PDM output on BP41, the pulse density is controlled by the contents of the
compare register in the same way as the PWM generation. Each of the pulses has a width equal to the counter clock
period.
PWM=0.25
PDM=0.25
PWM=0.75
PDM=0.75
Repetition period
96 11541
Figure 35. An example 4-bit PWM/PDM comparison
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