參數(shù)資料
型號： M44C510D-XXX-DOW
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER
封裝： SSOP-44
文件頁數(shù)： 16/60頁
文件大?。?/td> 709K
代理商： M44C510D-XXX-DOW
M44C510E
Preliminary Information
Rev. A1, 04-May-00
23 (60)
the interrupt edge and programming of the interrupt
priority levels. When programming or reprogramming ei-
ther of the port monitor control registers, any previously
generated interrupt on that port which has not yet been ac-
knowledged by the CPU or an interrupt generated by the
reprogramming itself is automatically cleared. Port A can
also be used for a mask programmable coded reset. For
more information see section 1.4 ’Hardware Reset’.
The Port Interrupt Priority Registers PAIPR and PBIPR
are I/O mapped to the the primary address registers of the
Port Monitor Module addresses ’2’h and ’3’h respec-
tively. The Port Interrupt Control Registers PAICR and
PBICR are mapped to the corresponding auxiliary
registers.
Port Monitor Interrupt Priority Register (PxIPR)
x = ’A’ (Port A) or ’B’ (Port B)
(Port A) Primary register address: ’2’hex
(Port B) Primary register address: ’3’hex
Bit 3
Bit 2
Bit 1
Bit 0
PxIPR
IMx
ITRx
PRx2
PRx1
Reset value: 1111b
IMx
– Interrupt Mask
ITRx
– Interrupt Transition
PRx2..1
– Interrupt Priority code
Table 10. Port Monitor Interrupt Priority Register (PxIPR)
Code
3 2 1 0
Function
x x 0 0
Port monitor interrupt priority 7
x x 0 1
Port monitor interrupt priority 5
x x 1 0
Port monitor interrupt priority 3
x x 1 1
Port monitor interrupt priority 1
x 0 x x
Port monitor interrupt on falling edge
x 1 x x
Port monitor interrupt on rising edge
0 x x x
Port monitor interrupt enabled
1 x x x
Port monitor interrupt disabled
Port Monitor Interrupt Control Register (PxICR)
x = ’A’ (Port A) or ’B’ (Port B)
(Port A) Auxiliary register address: ’2’hex
(Port B) Auxiliary register address: ’3’hex
Bit 3
Bit 2
Bit 1
Bit 0
PxICR
ENx3
ENx2
ENx1
ENx0
Reset value: 1111b
ENx3 ... 0 port monitor input ENable code
Table 11. Port Monitor Interrupt Control Register (PxICR)
Code
3 2 1 0
Function
x x x 0
Bit 0 can generate an interrupt
x x x 1
Bit 0 cannot generate an interrupt
x x 0 x
Bit 1 can generate an interrupt
x x 1 x
Bit 1 cannot generate an interrupt
x 0 x x
Bit 2 can generate an interrupt
x 1 x x
Bit 2 cannot generate an interrupt
0 x x x
Bit 3 can generate an interrupt
1 x x x
Bit 3 cannot generate an interrupt
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