參數(shù)資料
型號(hào)： M44C510D-XXX-DOW
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER
封裝： SSOP-44
文件頁(yè)數(shù)： 32/60頁(yè)
文件大小： 709K
代理商： M44C510D-XXX-DOW
M44C510E
Rev. A1, 04-May-00
Preliminary Information
38 (60)
Timer 0 Free Running Counter Modes (Strobe and 50% Duty Cycle)
In the free running counter mode, Timer 0 can be used as an event counter for summing external event pulses on BP40,
or as a timer with an internal time-based clock. When enabled, the counter will count up generating an output signal
on BP41 whenever the counter contents match the compare register (see figure 30). This signal can appear either as
a strobe pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode. Interrupts (if
not masked) are generated every 256 clocks on the overflow condition. The current counter state can be read at any
time by reading the capture register,. The compare register has no effect on the counter cycle time and will not influence
interrupts.
Timer
Clock
T0OUT1
(BP41)
Overflow
Interrupt
Timer = compare register (= 4)
Timer resets
on overflow
0
4
255
Timer
State
strobe
50% duty
cycle
1
2
35 6
4
1
2
35 6
0
255
4
1
2
35 6
0
96 11534
Figure 30. Timer 0 free running counter mode
Timer 0 Counter Reload Modes (Strobe and 50% Duty Cycle)
As in the free running mode, the counter can also be clocked from either an external signal on BP40 or from an internal
clock source. In this mode, the counter repetition period is completely defined by the contents of the compare register
(T0CP) (see figure 31). The counter counts up with the selected clock frequency. When it reaches the value held in
the compare register, the counter then returns to the zero state. At the same time, depending on the selected timer mode,
the BP41 either toggles or generates a strobe pulse. If the Timer 0 interrupt is unmasked, a compare interrupt is also
generated.
The resultant output frequency fOUT = fIN/2*(n+1) where
n = compare value (n = 1 – 255).
Timer
Clock
T0OUT1
(BP41)
Compare
Interrupt
Timer = compare register (= 7)
Resets timer
0
7
Timer
State
0
50% duty
cycle
strobe
4
1
2
35 6
7 0
4
1
2
35 6
7 0
4
1
2
35 6
96 11535
Figure 31. Timer 0 counter reload mode
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