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參數(shù)資料
| 型號： | M44C510D-XXX-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 封裝： | SSOP-44 |
| 文件頁數(shù)： | 41/60頁 |
| 文件大?。?/td> | 709K |
| 代理商： | M44C510D-XXX-DOW |
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M44C510E
Rev. A1, 04-May-00
Preliminary Information
46 (60)
Timer 1 Pulse Width Modulation
The Timer 1 generates the PWM signal by comparing the state of the free running up counter with the contents of the
compare register (see figure 42). If the result is less or equal to the compare register value, then the TIM1 output is
high. If the result is greater than the compare register value, then the TIM1 output is set low. Thus, the high phase of
the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space
ratios can be generated ranging from a continuous low signal over a variable pulse width signal. The PWM signal has
a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every compare event.
Care should be taken if SYSCL is used as the PWM clock source. The PWM output may stop if the CPU goes into
SLEEP depending on the programming of the NSTOP bit in the CM-register. Using this mode of operation recommends
to set the bit NSTOP =1.
Timer
Clock
T1OUT
(TIM1)
Timer = compare register (=4)
04
255
Timer
State
Compare
Interrupt
t_hi
t_low
t_hi = (comparator value)*clock period
t_low = (256-comparator value)* clock period
1
2
3
255
04
1
3
255
04
1
3
2
96 11548
Figure 42. Timer 1 pulse width modulation
2.6
Buzzer Module
The buzzer is a 4 stage frequency divider which divides the SUBCL and depending on the state of the Buzzer Control
Register (BZCR) can output one of four frequencies. An external piezo or buzzer can be driven by the complementary
buzzer outputs (BUZ and NBUZ) which are directed to Port 4 (BP42 and BP43) under control of the Timer/Counter
I/O Register (TCIOR) as shown in figure 28. When the buzzer is switched off, both of the buzzer outputs take up the
same logical state. This is controlled by the BZOP bit of the BZCR.
SUBCL
CK
BZCR
BZOF
BZFS2
BZOP
R
4 stage divider
SUBCL (32 kHz)
SUBCL / 4 (8 kHz)
SUBCL / 8 (4 kHz)
SUBCL / 16 (2 kHz)
BZFS1
R
BUZ
NBUZ
4 :1
MUX
96 11550
Figure 43. Buzzer module
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