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參數(shù)資料
| 型號： | M44C510D-XXX-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 封裝： | SSOP-44 |
| 文件頁數(shù)： | 30/60頁 |
| 文件大?。?/td> | 709K |
| 代理商： | M44C510D-XXX-DOW |
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M44C510E
Rev. A1, 04-May-00
Preliminary Information
36 (60)
Table 20. Timer 0 Interrupt Status Register (T0SR)
Code
3 2 1 0
Function
x x x 1
Timer 0 compare has occurred (Timer 0 = T0CP)
x x 1 x
Timer 0 overflow or underflow has occurred
x 1 x x
Timer 0 measurement completed
The interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding inter-
rupt is triggered. Therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked.
To see exactly when the flags are set, see T0MO control code table 18, page 34.
Reading from the timer/counter auxiliary register will access the Timer 0 Interrupt Status Register (T0SR).
Timer 0 Control Register (T0CR)
The T0CR is responsible for the predivision of the selected Timer 0 input clock (see TCCR). It can be divided or used
directly as clock for the up/down counter. Bit 0 is the mask bit for the Timer 0 interrupt.
Subport address (indirect write access): ’1’hex of Port address ’9‘hex
Bit 3
Bit 2
Bit 1
Bit 0
T0CR
T0FS3
T0FS2
T0FS1
T0IM
Reset value: 1111b
T0FS3 ... 1 – Timer 0 prescaler division factor code
T0IM – Timer 0 Interrupt Mask
Table 21. Timer 0 Control Register (T0CR)
Code
3 2 1 0
Function
x x x 1
Timer 0 interrupt disabled
x x x 0
Timer 0 interrupt enabled
0 0 0 x
Timer 0 prescaler divide by 256
0 0 1 x
Timer 0 prescaler divide by 128
0 1 0 x
Timer 0 prescaler divide by 64
0 1 1 x
Timer 0 prescaler divide by 32
1 0 0 x
Timer 0 prescaler divide by 16
1 0 1 x
Timer 0 prescaler divide by 8
1 1 0 x
Timer 0 prescaler divide by 4
1 1 1 x
Timer 0 prescaler bypassed
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