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參數(shù)資料
| 型號： | M44C510D-XXX-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 封裝： | SSOP-44 |
| 文件頁數(shù)： | 15/60頁 |
| 文件大?。?/td> | 709K |
| 代理商： | M44C510D-XXX-DOW |
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M44C510E
Rev. A1, 04-May-00
Preliminary Information
22 (60)
2.2.2
Bidirectional Port 5, Port 7 and Port C
All bidirectional ports except Port 0 and Port 1, include
a
bitwise-programmable
Data
Direction
Register
(PxDDR) which allows the individual programming of
each port bit as input or output. It also enables the reading
of the pin condition in output mode.
The bidirectional Ports 5, 7 and C as well as Port A and
Port B are equipped with the same standard I/O logic.
However, Port 5, Port 7 and Port C include standard
CMOS input stages, whereas Port A, Port B and all other
digital signal pins have Schmitt-trigger inputs. Port 5 and
Port 7 have high current output drive capability for up to
20 mA @ 5 V. Whereby the instantaneous sum of the out-
put currents should not exceed 100 mA.
Master reset
Q
BPxy
Mask options
*
PxDATy
PxDDRy
I/O Bus
D
I/O Bus
*
Pull-up
Pull-down
V
DD
*
Static
Pull-up
(Data out)
(Direction)
*
S
D
*
S
13381
V
DD
*
Static
Pull-down
30 k
W @ 5 V
Port A and Port B with Schmitt-trigger
Figure 19. Bidirectional Ports 5, 7, A, B and C
2.2.3
Bidirectional Port A and Port B with Port Monitor Function
PxICR
BPx3
BPx2
BPx1
BPx0
Decoder
Connected to Ports A and B (x = A or B)
INT5
INT7
INT3
INT1
INT5
INT7
INT3
INT1
PxIPR
ENx3
ENx2
ENx1
ENx0
IMAx
ITRx
PRx1
PRx2
00
01
10
11
PRx1 PRx2
16507
2 : 4
Figure 20. Port monitor module of Port A and Port B
In addition to the standard I/O functions described in sec-
tion 2.2.2, both Port A (BPA3 – BPA0) and Port B (BPB3
– BPB0) are equipped with Schmitt-trigger inputs and a
port monitor module. This module is connected across all
four port pins (see figure 20) and is intended for monitor-
ing those pins selected by control bits Enx3 – Enx0 and
generating an interrupt when the first pin leaves a prese-
lected logical default idle state. This state is defined by
control bit ITRx . Transitions on other pins will only cause
an interrupt if the other pins have first returned to the idle
state. This, for example is useful for interrupt initiated
port scanning without the power consuming task of con-
tinuously polling for port activity.
Using the Port Interrupt Control Register (PxICR), pins
can be individually selected. A non-selected pin cannot
generate an interrupt. The Port Interrupt Priority Register
(PxIPR) allows masking of each interrupt, definition of
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