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參數(shù)資料
| 型號： | M44C510D-XXX-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 封裝： | SSOP-44 |
| 文件頁數(shù)： | 21/60頁 |
| 文件大?。?/td> | 709K |
| 代理商： | M44C510D-XXX-DOW |
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M44C510E
Rev. A1, 04-May-00
Preliminary Information
28 (60)
2.3.1
Interval Timer Registers
The Interval Timer Frequency Select Register (ITFSR) is
I/O mapped to the primary address register of the pre-
scaler/ interval timer address (’F’hex) and the Interval
Timer Interrupt Priority Register (ITIPR) to the corre-
sponding auxiliary register. The interrupt masks MIA and
MIB enable interrupt masking of INTA and INTB respec-
tively. Each interrupt source can be programmed with
PRA and PRB to one of two interrupt priority levels. Dis-
abling both interrupts resets the interval timer.
Interval Timer Interrupt Priority Register (ITIPR)
Auxiliary register address (write only): ’F’hex
Bit 3
Bit 2
Bit 1
Bit 0
ITIPR
PRB
PRA
MIB
MIA
Reset value: 1111b
PRB – Priority select Interval Timer Interrupt INTB
PRA – Priority select Interval Timer Interrupt INTA
MIB – Mask Interval Timer Interrupt INTB
MIA – Mask Interval Timer Interrupt INTA
Table 13.
Interval Timer Interrupt Priority Register (ITIPR)
Code
3 2 1 0
Function
x x 1 1
Reset prescaler and halt
x x x 1
Interrupt A disabled
x x x 0
Interrupt A enabled
x x 1 x
Interrupt B disabled
x x 0 x
Interrupt B enabled
x 1 x x
Interrupt A => priority 1
x 0 x x
Interrupt A => priority 5
1 x x x
Interrupt B => priority 2
0 x x x
Interrupt B => priority 6
Interval Timer Frequency Select Register (ITFSR)
Primary register address (write only): ’F’hex
Bit 3
Bit 2
Bit 1
Bit 0
ITFSR
FS3
FS2
FS1
FS0
Reset value: 1111b
FS3 ... 0 – Frequency select code
Table 14. Interval Timer Frequency Select Register (ITFSR)
Code
3 2 1 0
Function
SUBCL
divide by
SUBCL
= 32 kHz
Code
3 2 1 0
Function
SUBCL
divide by
SUBCL
= 32 kHz
0 0 0 0
INTA
215
Select 1 Hz
1 0 0 0
INTB
212
Select 8 Hz
0 0 0 1
214
Select 2 Hz
1 0 0 1
211
Select 16 Hz
0 0 1 0
213
Select 4 Hz
1 0 1 0
29
Select 64 Hz
0 0 1 1
212
Select 8 Hz
1 0 1 1
27
Select 256 Hz
0 1 0 0
211
Select 16 Hz
1 1 0 0
25
Select 1024 Hz
0 1 0 1
210
Select 32 Hz
1 1 0 1
24
Select 2048 Hz
0 1 1 0
29
Select 64 Hz
1 1 1 0
23
Select 4096 Hz
0 1 1 1
28
Select 128 Hz
1 1 1 1
22
Select 8192 Hz
The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the select code (FS2–FS0).
This allows independent programming of interval times for INTA and INTB.
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