參數(shù)資料
型號： M44C510D-XXX-DOW
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER
封裝： SSOP-44
文件頁數(shù)： 4/60頁
文件大?。?/td> 709K
代理商： M44C510D-XXX-DOW
M44C510E
Rev. A1, 04-May-00
Preliminary Information
12 (60)
1.4
Hardware Reset
The master reset forces the CPU into a well-defined
condition, is unmaskable and is activated independent of
the current program state. It can be triggered by either
initial supply power-up, a short collapse of the power sup-
ply, a watchdog time out, activation of the NRST input or
the occurrence of a coded reset on Port A (see figure 9).
A master reset activation will reset the interrupt enable
flag, the interrupt pending registers, the interrupt active
registers and initialize all on-chip peripherals.
When the reset condition disappears, the CPU remains re-
set for a further reset delay time (approx. 80 ms), after
which it continues with a short call instruction (opcode
C1h) to the ROM address 008h. This activates the initial-
ization routine $RESET which in turn initializes all
necessary RAM variables, stack pointers and peripheral
configuration registers.
Power-on Reset
The fully integrated power-on reset circuit ensures that
the core is held in a reset state until the minimum operat-
ing supply voltage has been reached. A reset condition is
also
generated
should
the
supply
voltage
drop
momentarily below the minimum operating supply.
External Reset (NRST)
An external reset can be triggered with the NRST pin. To
activate an external reset, the pin should be low for a
minimum of 4
ms.
Coded Reset (Port A)
The coded reset circuit is connected directly to the Port A
terminals. By using a mask option, the user can define a
hardwired code combination (e.g., all pins low) which, if
occurring on the Port A, will generate a reset in the same
way as the NRST pin.
Table 4. Multiple key reset options
NO_RST
Not used (default)
RST2
BPA0 & BPA1 = low
RST3
BPA0 & BPA1 & BPA2 = low
RST4
BPA0 & BPA1 & BPA2 & BPA3 = low
RST5
BPA0 & BPA1 = high
RST6
BPA0 & BPA1 & BPA2 = high
RST7
BPA0 & BPA1 & BPA2 & BPA3 = high
Note, that if this option is used, the reset is not maskable
and will also trigger if the predefined code is written on
to the Port A by the CPU itself. Care should also be taken
not to generate an unwanted reset by inadvertently pass-
ing through the reset code on input transitions. This
applies especially if the pins have a high capacitive load.
Watchdog Reset
The watchdog’s function can be enabled via a mask op-
tion and triggers a reset with every watchdog counter
overflow. To suppress the watchdog reset, the counter
must be regularly reset by reading the watchdog timer
register address (CWD).
The CPU reacts in exactly the same manner as a reset
stimulus from any of the above sources.
Port A
I/O
reset code
CPU
NRST
V
Watch-
Power-on
reset
CPU reset
rst
Pull-up
CODE *
time out
V
WD reset
* = Mask option
dog *
DD
SS
DD
16506
Reset delay
timer
Figure 9. Reset configuration
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