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參數(shù)資料
| 型號： | M44C510D-XXX-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 封裝： | SSOP-44 |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 709K |
| 代理商： | M44C510D-XXX-DOW |
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M44C510E
Preliminary Information
Rev. A1, 04-May-00
43 (60)
2.5.4
Timer 1 Modes
The Timer 1 is aimed at performing event counting and
timing functions (see figure 27). It has, unlike the
Timer 0, no gated clock or externally triggered capture
modes. The counter counts up with an internal or external
clock, depending on the state of the Timer 1 Control Reg-
ister (T1CR) and the Timer/Counter Clock Control
Register (TCCR) and generates a compare interrupt
whenever the counter matches the Timer 1 compare regis-
ter. This is the only Timer 1 interrupt source. Masking can
be performed using the mask bit in the Timer 1 Control
Register (T1CR) and priority can be defined in the Timer/
Counter Interrupt Priority Register (TCIP). The TIM1 pin
is used by the Timer 1 either as clock/event input or timer
output. I/O control of the Timer 1 pin TIM1 is controlled
entirely by the hardware, therefore if the TIM1 is selected
as an external clock or event source (in the TCCR), there
can be no Timer 1 signal output. In this case, the timer
would be used solely to generate interrupts.
In autostop operation, the Timer 1 will halt both itself and
Timer 0 whenever the Timer 1 compare value is reached.
This feature can be used for example to generate an exact
burst of pulses. Both timers will remain stopped until
restarted. Restarting is performed in the normal way by
setting the appropriate control bits in the Timer/Counter
Mode Register (TCM0).
Timer 1 Mode Register (T1MO)
Subport address (indirect write address): ’2’hex of Port address ’9‘hex
Bit 3
Bit 2
Bit 1
Bit 0
T1MO
T1MO3
T1MO2
T1MO1
T1MO0
Reset value: 1111b
T1MO3 ... 0 – Timer 1 Mode Control
Table 22. Timer 1 Mode Register (T1MO)
Code
3 2 1 0
Function
Compare
Interrupt
x x 0 0
Counter free running (50% duty cycle)
yes
x x 0 1
Counter auto reload (50% duty cycle)
yes
x x 1 0
Pulse width modulation
yes
x x 1 1
Counter auto-reload (strobe output)
yes
x 0 x x
Increment on falling edge of clock
–
x 1 x x
Increment on rising edge of clock
–
1 x x x
Normal operation (no autostop)
yes
0 x x x
Autostop operation (Timer 1 stops Timer 2)
yes
Timer 1 Control Register (T1CR)
The T1CR is responsible for the predivision of the selected Timer 1 input clock (see TCCR). It can be divided or used
directly as clock for the up counter. Bit 0 is the mask bit for the Timer 1 interrupt.
Subport address (indirect write access): ’3’hex of Port adress ’9‘hex
Bit 3
Bit 2
Bit 1
Bit 0
T1CR
T1FS3
T1FS2
T1FS1
T1IM
Reset value: 1111b
T1FS3 ... 1
– Timer 1 Prescaler Division Factor Code
T1IM
– Timer 1 Interrupt Mask
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