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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 97/250頁(yè) |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O
read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host
CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register
is only available in EPP mode.
EPP Data Port 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is
cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus
DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle
causes an EPP DATA WRITE cycle to be performed, during which the data is latched for the duration
of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle
causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of
DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP
mode.
EPP Data Port 1
ADDRESS OFFSET = 05H
The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA
PORT 0 for a description of operation. This register is only available in EPP mode.
EPP Data Port 2
ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA
PORT 0 for a description of operation. This register is only available in EPP mode.
EPP Data Port 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA
PORT 0 for a description of operation. This register is only available in EPP mode.
EPP 1.9 Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is
in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by
the SPP Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed
from the start of the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the
current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to
always be in a write mode and the nWRITE signal to always be asserted.
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