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參數(shù)資料
| 型號： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁數(shù)： | 44/250頁 |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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Non-DMA Mode - Transfers from the FIFO to the Host
The interrupt and RQM bits in the Main Status Register are activated when the FIFO contains (16-
<threshold>) bytes or the last bytes of a full sector have been placed in the FIFO. The interrupt can be
used for interrupt-driven systems, and RQM can be used for polled systems. The host must respond
to the request by reading data from the FIFO. This process is repeated until the last byte is
transferred out of the FIFO. The FDC will deactivate the interrupt and RQM bit when the FIFO
becomes empty.
Non-DMA Mode - Transfers from the Host to the FIFO
The interrupt and RQM bit in the Main Status Register are activated upon entering the execution phase
of data transfer commands. The host must respond to the request by writing data into the FIFO. The
interrupt and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO
has <threshold> bytes remaining in the FIFO. The FDC enters the result phase after the last byte is
taken by the FDC from the FIFO (i.e. FIFO empty condition).
DMA Mode - Transfers from the FIFO to the Host
The FDC generates a DMA request cycle when the FIFO contains (16 - <threshold>) bytes, or the last
byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the
request by reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO
becomes empty by generating the proper sync for the data transfer.
DMA Mode - Transfers from the Host to the FIFO.
The FDC generates a DMA request cycle when entering the execution phase of the data transfer
commands. The DMA controller must respond by placing data in the FIFO. The DMA request
remains active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has
<threshold> bytes remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating
that no more data is required.
Data Transfer Termination
The FDC supports terminal count explicitly through the TC cycle and implicitly through the
underrun/overrun and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can
define the last sector to be transferred in a single or multi-sector transfer.
If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-
sector, and the FDC will continue to complete the sector as if a hardware TC cycle was received.
The only difference between these implicit functions and TC cycle is that they return "abnormal
termination" result status. Such status indications can be ignored if they were expected.
Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be
complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the
removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes
from the FIFO. The host must tolerate this delay.
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