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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 127/250頁(yè) |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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127
Soft Power Down Mode
This mode is entered by executing a HALT instruction. The execution of program code is halted until
either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this
mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes
with a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using
RESET then a normal reset sequence is initiated and program execution starts from program memory
location 0.
Hard Power Down Mode
This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the
oscillator driver cell. When either RESET is driven active or a data byte is written to the DBBIN
register by a master CPU, this mode will be exited (as above). However, as the oscillator cell will
require an initialization time, either RESET must be held active for sufficient time to allow the oscillator
to stabilize. Program execution will resume as above.
Interrupts
The LPC47B34x provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.
Memory Configurations
The LPC47B34x provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
Register Definitions
Host I/F Data Register
The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will
load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of
this register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF
flag. Refer to the KIRQ and Status register descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide. Table 46 shows the contents of the Status register.
Table 46 - Status Register
D4
UD
D7
UD
D6
UD
D5
UD
D3
C/D
D2
UD
D1
IBF
D0
OBF
Status Register
This register is cleared on a reset. This register is read-only for the Host and read/write by the
LPC47B34x CPU.
UD
C/D
Writable by LPC47B34x CPU. These bits are user-definable.
(Command Data)-This bit specifies whether the input data register contains data or a
command (0 = data, 1 = command). During a host data/command write operation, this bit is
set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.
(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input
data register. Setting this flag activates the LPC47B34x CPU's nIBF (MIRQ) interrupt if
enabled. When the LPC47B34x CPU reads the input data register (DBB), this bit is
automatically reset and the interrupt is cleared. There is no output pin associated with this
internal signal.
IBF
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