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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 22/250頁(yè) |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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22
DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47B34x. DMA
write cycles involve the transfer of data from the LPC47B34x to the host (main memory). Data will be
coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the
LPC47B34x are 1 byte.
See the
Low Pin Count (LPC) Interface Specification
Reference, Section 6.4, for the field definitions
and the sequence of the DMA Read and Write cycles.
DMA Protocol
DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47B34x and special
encodings on LAD[3:0] from the host.
The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification
Reference.
Power Management
CLOCKRUN Protocol
The nCLKRUN pin is not implemented in the LPC47B34x.
See the
Low Pin Count (LPC) Interface Specification
Reference, Section 8.1.
LPCPD Protocol
See the
Low Pin Count (LPC) Interface Specification
Reference, Section 8.2.
SYNC Protocol
See the
Low Pin Count (LPC) Interface Specification
Reference Section 4.2.1.8 for a table of valid
SYNC values.
Typical Usage
The SYNC pattern is used to add wait states. For read cycles, the LPC47B34x immediately drives the
SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write
cycles. If the LPC47B34x needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0]
until it is ready, at which point it will drive 0000 or 1001. The LPC47B34x will choose to assert 0101
or 0110, but not switch between the two patterns.
The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.
The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete
within a few clocks. The LPC47B34x uses a SYNC of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is
provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond).
However, the LPC47B34x uses a SYNC of 0110 for all wait states in an I/O transfer.
The SYNC value is driven within 3 clocks.
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