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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 114/250頁(yè) |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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Programmed I/O - Transfers from the FIFO to the Host
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are
available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst,
otherwise readIntrThreshold bytes may be read from the FIFO in a single burst.
readIntrThreshold =(16-<threshold>) data bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or
equal to (16-<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16
bytes in the FIFO). The host must respond to the request by reading data from the FIFO. This
process is repeated until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it
can be completely emptied in a single burst, otherwise a minimum of (16-<threshold>) bytes may be
read from the FIFO in a single burst.
Programmed I/O - Transfers from the Host to the FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or
more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before
the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes.
writeIntrThreshold = (16-<threshold>) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or
equal to <threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less
bytes of data in the FIFO.) The host must respond to the request by writing data to the FIFO. If at this
time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-
<threshold>) bytes may be written to the FIFO in a single burst. This process is repeated until the last
byte is transferred into the FIFO.
PARALLEL PORT FLOPPY DISK CONTROLLER
The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is
selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2.
These modes can be selected in the Parallel Port Mode Register, as defined in the Parallel Port Mode
Register, Logical Device 3, at 0xF1. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has
drive 0 and 1 on the parallel port pins.
The following parallel port pins are read as follows by a read of the parallel port register:
1. Data Register (read) = last Data Register (write)
2. Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1
3. Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1
The following FDC pins are all in the high impedence state when the PPFDC is actually selected by
the drive select register:
1.
nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1.
2.
If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode
is selected.
The FDC signals are muxed onto the Parallel Port pins as shown in Table 40.
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