
86
(b)
Character times are calculated by using the RCLK input for a clock signal (this makes the
delay proportional to the baud rate).
When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads
one character from the RCVR FIFO.
When a timeout interrupt has not occurred the timeout timer is reset after a new character is
received or after the CPU reads the RCVR FIFO.
(c)
(d)
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT
interrupts occur as follows:
(a)
The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is
cleared as soon as the transmitter holding register is written to (1 of 16 characters may be
written to the XMIT FIFO while servicing this interrupt) or the IIR is read.
The transmitter FIFO empty indications will be delayed 1 character time minus the last stop
bit time whenever the following occurs: THRE=1 and there have not been at least two bytes
at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt
after changing FCR0 will be immediate, if it is enabled.
(b)
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current
received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter
holding register empty interrupt.
FIFO Polled Mode Operation
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled
Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can
be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER
status via the LSR. LSR definitions for the FIFO Polled Mode are as follows:
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the
RCVR and XMIT FIFOs are still fully capable of holding characters.