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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 17/250頁(yè) |
| 文件大小： | 645K |
| 代理商： | LPC47B34X |
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17
Trickle Power Functionality
When the LPC47B34x is running under VTR only, the following functionality is retained:
PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The
following lists the wakeup events:
UART 1 Ring Indicator
UART 2 Ring Indicator
Keyboard data
Mouse data
nRING
Wake on Specific Key Logic
Intrusion
GPIOs for wakeup. See below.
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.
I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0),
these pins may only be configured as inputs. These inputs have input buffers into the wakeup
logic that are powered by VTR.
I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0),
are powered by VTR. This means at a minimum, they will source their specified current from VTR
even when VCC is present.
The GPIOs that are used for PME wakeup are GP10-GP17, GP20- GP27, GP32-GP33, GP36, GP37,
GP41, GP42, GP43-GP45, GP50, GP56-GP57, GP60, GP61, GP65, GP70-77, GP80-82, GP85-86.
These GPIOs function as follows (with the exception of GP42, GP65 and GP86 - see below):
Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not
impose a load on any external VTR powered circuitry). They are wakeup compatible inputs under
VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.
All GPIOs listed above are for PME wakeup. GP50 can be used for PME wakeup only if nRI2 function
is selected. GP42 has the nIO_PME output pin function.
The other GPIOs function as follows:
GP34, GP35, GP40, GP46, GP51-GP55, GP62, GP63, GP64, GP83 and GP84:
Buffers powered by VCC, but in the absence of VCC they are backdrive protected.
These pins are not used for wakeup.
GP30, GP31, GP42, GP65, GP66, GP67, GP86:
Buffer is powered by VTR.
GP42 has the IO_PME pin function.
GP66 and GP67 are not used for wakeup.
See the Table in the GPIO section for more information.
The IRTX pin (TXD2/GP53) is driven low on VCC POR and Hard Reset regardless of the selected pin
function. The TXD2/GP53 pin will remain low following a VCC POR until the serial port is enabled by
setting the activate bit, at which time the pin will reflect the state of the UART2 transmit output. If the
IRTX function is selected for the pin, the pin will reflect the state of the IR transmit output of the IRCC
block when the serial port is enabled by setting the activate bit. If the GPIO output function is
selected, the pin will reflect the state of the data bit.
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