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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁數(shù)： | 43/250頁 |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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43
Model 30 mode
- (IDENT low, MFM low)
This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR
becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.
DMA Transfers
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a
DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA
transfer modes: Single Transfer and Burst Transfer. Burst mode is enabled via Logical Device 0-
CRF0-Bit[1] (LD0-CRF0[1]).
Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution,
and Result. Each phase is described in the following sections.
Command Phase
After a reset, the FDC enters the command phase and is ready to accept a command from the host.
For each of the commands, a defined set of command code bytes and parameter bytes has to be
written to the FDC before the command phase is complete. (Please refer to Table 16 for the command
set descriptions). These bytes of data must be transferred in the order prescribed.
Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register.
RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM
is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts
RQM again to request each parameter byte of the command unless an illegal command condition is
detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically
enters the next phase as defined by the command definition.
The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid
Command" condition.
Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or
non-DMA mode as indicated in the Specify command.
After a reset, the FIFO is disabled. Each data byte is transferred by read/write or DMA cycle
depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO
threshold value.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions,
<threshold> is defined as the number of bytes available to the FDC when service is requested from the
host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and
ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires
faster servicing of the request for both read and write cases. The host reads (writes) from (to) the
FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to
the service request. This is the desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period
after a service request, but results in more frequent service requests.
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