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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 74/250頁(yè) |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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74
Table 26 – Effects of WGATE and GAP Bits
WGATE
0
0
GAP
0
1
MODE
LENGTH OF
GAP2 FORMAT
FIELD
22 Bytes
22 Bytes
PORTION OF
GAP 2
WRITTEN BY
WRITE DATA
OPERATION
0 Bytes
19 Bytes
1
1
0
1
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
22 Bytes
41 Bytes
0 Bytes
38 Bytes
LOCK
In order to protect systems with long DMA latencies against older application software that can disable
the FIFO the LOCK Command has been added. This command should only be used by the FDC
routines, and application software should refrain from using it. If an application calls for the FIFO to
be disabled then the CONFIGURE command should be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the
CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to
logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the
previously set parameters to their default values. All "hardware" RESET from the nPCI_RESET pin
will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values.
A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of
the LOCK bit set by the command byte.
Enhanced DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application
software development and debug. To accommodate the LOCK command and the enhanced
PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified
to contain the additional data from these two commands.
Compatibilty
The LPC47B34x was designed with software compatibility in mind. It is a fully backwards- compatible
solution with the older generation 765A/B disk controllers. The FDC also implements on-board
registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller
subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a
PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM
bits are configured by the system BIOS.
Direct Support for Two Floppy Drives
The nMTR1 function is on pin 58. nMTR1 is the second alternate function on this GPIO pin (GP36).
The nMTR1 function is controllable as open drain or push pull as nMTR0 is through bit 6 of the FDD
Mode Register in CRF0 of LD 0. This overrides the selection of the output type through bit 7 of the
GPIO control register. It is also controlled by bit 7 of the FDD Mode Register.
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