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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 126/250頁(yè) |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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KIRQ
If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The
KIRQ signal can be connected to system interrupt to signify that the LPC47B34x CPU has written to
the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up,
after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally
reflects the status of writes "DBB". (KIRQ is normally selected as IRQ1 for keyboard support.)
If "EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to
P24 forces KIRQ low; a high forces KIRQ high.
MIRQ
If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The
MIRQ signal can be connected to system interrupt to signify that the LPC47B34x CPU has read the
DBB register. If "EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25
forces MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support).
Gate A20
A general purpose P21 is used as a software controlled Gate A20 or user defined output.
8042 PINS
The 8042 functions P17, P16 and P12 are implemented as in a true 8042 part. Reference the 8042
spec for all timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable
signal to drive the output to 1 within 20-30nsec. After 500nsec (six 8042 clocks) the port enable goes
away and the external pull-up maintains the output signal as 1.
In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode,
the port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is
1, the output tristates: an external pull-up can pull the pin high, and the pin can be shared. In 8042
mode, the pins cannot be programmed as input nor inverted through the GP configuration registers.
External Keyboard and Mouse Interface
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data
transmission. Several sources also supply PS/2 mouse products that employ the same type of
interface. To facilitate system expansion, the LPC47B34x provides four signal pins that may be used
to implement this interface directly for an external keyboard and mouse.
The LPC47B34x has four high-drive, open-drain output, bidirectional port pins that can be used for
external serial interfaces, such as external keyboard and PS/2-type mouse interfaces. They are KCLK,
KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0.
P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output
as MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT
pin is connected to P11. NOTE: External pull-ups may be required.
Keyboard Power Management
The keyboard provides support for two power-saving modes: soft powerdown mode and hard
powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter
and interrupts are still active. In hard power down mode the clock to the 8042 is stopped.
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