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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 93/250頁(yè) |
| 文件大小： | 645K |
| 代理商： | LPC47B34X |
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IR Transmit Pins
The following description pertains to the IRTX (TXD2/GP53) and IRTX2 (GP35/IRTX2) pins of the
LPC47B34x.
Following a VTR POR, VCC POR and hard reset, the GP53 register defaults to the TXD2 function as a
push-pull output, and the GP53 data bit (bit 3 of the GP5 register) is reset. Therefore, following a
VCC POR, the IRTX pin (TXD2/GP53) will be output and low. It will remain low until one of the
following conditions are met:
TXD2/IRTX/GP53 Pin. This pin defaults to the TXD2 function.
1. This pin will remain low following a VCC POR until the TXD2 function is selected for the pin AND
Serial Port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the
IR transmit output of the IR block (if IR is enabled through the IR Options Register for Serial Port
2).
2. This pin will remain low following a VCC POR until the TXD2 function is selected for the pin AND
Serial Port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the
transmit output of serial port 2.
3. This pin will remain low following a VCC POR until the corresponding GPIO data bit (GP5 register
bit 3) is set or the polarity bit in the GP53 control register is set.
GP35/IRTX2 Pin. This pin defaults to the GPIO Output function. This pin does not have same default
condition as IRTX pin. The GP35 register defaults to a GPIO push-pull output on VTR POR and the
GP35 data bit (bit 5 of the GP3 register) defaults to ‘1’ on VTR POR, VCC POR and hard reset.
Therefore, this pin defaults to an active high output on VTR POR, VCC POR and Hard Reset. This pin
and the GP34/IRRX2 pin are not recommended to be used for IR functionality. See the GPIO section.
PARALLEL PORT
The LPC47B34x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2
type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities
Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling,
power down, changing the base address of the parallel port, and selecting the mode of operation.
The LPC47B34x also provides a mode for support of the floppy disk controller on the parallel port.
The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to
the parallel port due to printer power-up.
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their
associated registers and control gating. The control and data port are read/write by the CPU, the
status port is read/write in the EPP mode. The address map of the Parallel Port is shown on the
following page.
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