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參數(shù)資料
| 型號： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁數(shù)： | 123/250頁 |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency
could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could
cause a system fault. The host interrupt controller is responsible for ensuring that these latency
issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt
controller by the same amount as the SER_IRQ Cycle latency in order to ensure that these events do
not occur out of order.
AC/DC Specification Issue
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI
bus clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will
follow PCI spec. section 4, sustained tri-state.
Reset and Initialization
The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents
while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode.
The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data
default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse
width) for subsequent SER_IRQ Cycles. It is Host Controller’s responsibility to provide the default
values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ
system suspend, insertion, or removal application, the Host controller should be programmed into
Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system
configuration changes.
ISA IRQ To Serial IRQ Conversion Capability
Pins 100-110 have the ISA IRQs muxed onto the GPIO pins as inputs. If the IRQ function is chosen
for these pins via the GPIO registers, then the associated IRQ input will appear in the serial IRQ
stream if the IRQ is not used by an internal device. The ISA IRQs that are supported for this
functionality are IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, IRQ15. See
the GPIO section for configuration information.
The internal IRQs that are used for the devices in the part are given precedence over the IRQs on the
GPIO pins. That is, if the IRQx is selected for a logical device in the part through register 0x70, and it
is enabled for use (see description below), then if the same IRQx is programmed on its assocated
GPIO pin, the external IRQx will be blocked from the serial IRQ frame. If however the IRQx is
selected for a logical device in the part through register 0x70, and it is NOT enabled for use, then if the
same IRQx is programmed on its associated GPIO pin, this external IRQ will go onto the serial IRQ
frame. Therefore, if an IRQ is selected for the logical device through register 0x70, then the enable bit
for the device, if present, is used to control whether the internal IRQ or the external IRQ on a GPIO is
placed onto the serial stream. The following devices have an enable bit: FDC, UART 1, UART2,
UART3 and the parallel port. The following devices do not have an enable bit: keyboard, mouse,
WDT. For these devices, the interrupt is enabled as follows: programming an IRQ in register 0x70 of
logical device 7 enables the keyboard interrupt, programming an IRQ in register 0x72 of logical device
7 enables the mouse interrupt and programming an interrupt in the WDT_CFG register enables the
WDT interrupt.
User Note: In order to use the ISA IRQs muxed onto the GPIO pins, the corresponding IRQ must not
be used for any of the devices in the LPC47B34x.
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