參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 64/102頁(yè)
文件大小： 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
64
PRELIMINARY
4.3.8.
DRAM REFRESH
MTXC supports CAS-before-RAS# (CBR) refresh and Self refresh. The refresh rate is controlled via the
DRAM Refresh Rate field in the DRAM Control Register (DRAMC). When a refresh request is generated, it is
placed in a four entry queue. The DRAM controller services a refresh request when the refresh queue in not
empty and the controller has no other requests pending. When the refresh queue is full, refresh becomes the
highest priority request and will be serviced next by the controller.
Refresh is only performed on rows that are populated (i.e., “smart refresh”). The controller determines which
rows are populated by looking at the DRB registers. Note that Refresh has to be disabled before the refresh
rate is changed.
Refer to bit 5 in the MCTL register (offset 79h) for suspend refresh information.
4.4.
PCI CLK Control (CLKRUN#)
4.4.1.
CLOCKING STATES
There are three main states in the clocking protocol:
Clock Running:
The clock is running and the bus is operational.
About to Stop:
The central resource has indicated on the CLKRUN# line that the clock is about to stop.
Clock Stopped:
The clock is stopped with CLKRUN# being monitored for a restart
4.4.2.
OPERATION
The MTXC is a CLKRUN# Master device and behaves according to the rules for a master device. The PIIX4
companion chip controls the clocks in the system and is the CLKRUN# Central Resource. Please refer to the
latest “PCI Mobile Design Guide” for more information.
4.5.
SMRAM Memory Space
The MTXC supports the use of main memory as System Management RAM (SMRAM), enabling the use of
System Management Mode. The MTXC supports two SMRAM options; Compatible SMRAM (C_SMRAM)
and Extended SMRAM (E_SMRAM).
4.5.1.
COMPATIBLE SMRAM (C_SMRAM)
This is the traditional SMRAM feature supported in Intel PCIsets. When this function is enabled via
C_BASE_SEG[2:0]=010 and G_SMRAME=1 of the SMRAMC register, the MTXC reserves 000A0000h
through 000BFFFFh (A and B segments) of the main memory for use as Noncacheable SMRAM. CPU
accesses to segments A and B while not in SMM (i.e., SMIACT# is negated) are always forwarded to the PCI
bus. CPU accesses to segments A and B while in SMM (i.e., SMIACT# is asserted) are forwarded to either
DRAM or PCI bus, depending on the value of bits[6:0] of the SMRAMC register. PCI masters cannot access
the SMRAM area of the main memory. When a PCI master tries to access the SMRAM space, the MTXC
does not respond to the PCI cycle (i.e., DEVSEL# is not asserted).
4.5.2.
EXTENDED SMRAM (E_SMRAM)
This feature in the MTXC extends the SMRAM space up to 1 Mbytes and provide writeback cacheability. This
feature requires that SMI handlers execute above 1 Mbytes which will require rewriting the existing code to
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