Extended Temperature 82439TX (MTXC) Datasheet
3
PRELIMINARY
CONTENTS
PAGE
1. 0. ARCHITECTURE OVERVIEW..............................................................................................................6
2. 0. SIGNAL DESCRIPTION .......................................................................................................................9
2.1.
MTXC Signals ..................................................................................................................................9
2.1.1. HOST INTERFACE........................................................................................................................9
2.1.2. DRAM Interface...........................................................................................................................11
2.1.3. SECONDARY CACHE INTERFACE............................................................................................13
2.1.4. PCI INTERFACE .........................................................................................................................14
2.1.5. TEST AND CLOCK......................................................................................................................15
2.1.6. POWER MANAGEMENT.............................................................................................................15
2.1.7. POWER AND GROUND PINS.....................................................................................................15
2.2.
MTXC Strapping Options................................................................................................................16
2.3.
Power Planes.................................................................................................................................16
2.4.
Power Sequencing Requirements ..................................................................................................17
2.5.
Improving Signal Integrity in Lightly Loaded Systems.....................................................................18
2.6.
Signal States During And After A Hard Reset.................................................................................18
3. 0. REGISTER DESCRIPTION.................................................................................................................20
3.1.
I/O Mapped Registers.....................................................................................................................20
3.1.1. PM2_CNTRL
PM2 REGISTER BLOCK.....................................................................................21
3.1.2. CONFADD
CONFIGURATION ADDRESS REGISTER.............................................................21
3.1.3. CONFDATA
CONFIGURATION DATA REGISTER ..................................................................22
PCI Configuration Space Mapped Registers......................................................................................22
3.1.4. VID
VENDOR IDENTIFICATION REGISTER............................................................................25
3.1.5. DID
DEVICE IDENTIFICATION REGISTER .............................................................................25
3.1.6. PCICMD
PCI COMMAND REGISTER ......................................................................................25
3.1.7. PCISTS
PCI STATUS REGISTER............................................................................................26
3.1.8. RID
REVISION IDENTIFICATION REGISTER..........................................................................27
3.1.9. CLASSC
CLASS CODE REGISTER.........................................................................................27
3.1.10. MLT
MASTER LATENCY TIMER REGISTER.........................................................................27
3.1.11. HEDT
HEADER TYPE REGISTER .........................................................................................28
3.1.12. BIST
BIST REGISTER............................................................................................................28
3.1.13. ACON
ARBITRATION CONTROL REGISTER........................................................................28
3.1.14. PCON
PCI CONTROL REGISTER..........................................................................................29
3.1.15. CC
CACHE CONTROL REGISTER ........................................................................................29
3.1.16. CEC
EXTENDED CACHE CONTROL REGISTER..................................................................31
3.1.17. SDRAMC
SDRAM CONTROL REGISTER..............................................................................32
3.1.18. DRAMEC
DRAM EXTENDED CONTROL REGISTER............................................................34
3.1.19. DRAMC
DRAM CONTROL REGISTER ..................................................................................35
3.1.20. DRAMT
DRAM TIMING REGISTER........................................................................................36