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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 55/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
55
PRELIMINARY
Rules for Populating SIMM Modules (or x32 SO-DIMM modules)
SIMM sockets can be populated in any order (i.e., memory for RAS0# does not have to be populated
before memory for RAS[2:1]# or RAS[4:3]# are used).
SIMM socket pairs (i.e., two, 32-bit wide SIMMs) need to be populated with the same densities. For
example, SIMM sockets for RAS0# should be populated with identical densities. However, SIMM sockets
for RAS[2:1]# can be populated with different densities than the SIMM socket pair for RAS0#.
EDOs and standard page mode can both be used; however, only one type should be used per SIMM
socket pair. For example, in the table shown below SIMM sockets for RAS[2:1]# can be populated with
EDOs while SIMM sockets for RAS[4:3]# can be populated with standard page mode. If different memory
is used for different rows, each row will be optimized for that type of memory.
The DRAM Timing Register which provides the DRAM speed grade control for the entire memory array
must be programmed to use the timings of the slowest DRAMs installed.
Rules for Populating DIMM or SO-DIMM modules
DIMM or SO-DIMM sockets can be populated in any order (i.e., memory for RAS0# does not have to be
populated before memory for RAS[2:1]# or RAS[4:3]# are used).
4.3.2.
CONFIGURATION REQUIREMENTS
General Configuration Requirements
In a system that uses 64-Mbit SDRAM, the RAS4#/CS4#/BA1 and RAS5#/CS5#/MA13 signals are used
to provide two additional address lines (BA1 and MA13), and KRQAK/CS4_64# is used to provide the 5th
CS# line, if required. To enable 64-Mbit support for four rows of SDRAM, set SDRAMC[bit 1] to 1 (offset
54h). To enable 64-Mbit support for five rows of SDRAM, SDRAMC[bit 1] must be set to 1, and DRAM
cache must
not
be present in the system (indicated by CEC[bit 5]=0, offset 53h). In a five row SDRAM
system that supports 64-Mbit SDRAM devices, the KRQAK/CS4_64# signal provides the fifth CS# (or
CS4_64#) function. This means that a system that supports DRAM Cache, can not support five rows of
64-Mbit SDRAM. However, four rows of 64-Mbit SDRAM with DRAM Cache is supported. In a FPM/EDO
only configuration, there are no restrictions on using 64-Mbit devices (i.e., all six rows can support 64-
Mbit DRAM devices. However, SDRAMC[bit 1] must be set to 1 if more than four rows of EDO/FPM are
used. This allows the RAS4# and RAS5# functions to be used.
Driven on
RAS5#/CS5#/
MA13
Driven on
RAS4#/CS4#/
MA13
Driven on
KRQAK/
CS4_64#
64-Mbit
(SDRAM)
64-Mbit
(EDO/FPM)
Bit 1, reg 54h=0
RAS5#/CS5#
RAS4#/CS4#
KRQAK
no
yes (6 rows)
Bit 1, reg 54h=1 and
DRAM Cache is
present*
MA13
BA1 (Bank Select)
KRQAK
Yes
(4 rows)
Yes (4 rows)
Bit 1, reg 54h=1 and
DRAM Cache is not
present
1
MA13
BA1 (Bank Select)
RAS4#/
CS4_64#
Yes
(5 rows)
Yes (5 rows)
NOTES:
1.
The presence of DRAM cache is indicated by the value in bit 5, register 53h.
Due to loading, using SDRAM x4 devices is not recommended.
Buffering of SDRAM Rows is not supported
In a five row system, the 5th row is intended to be implemented with DRAM devices that are soldered
down on the motherboard. If a DIMM or a SIMM is used in the 5th row, it should
not
be used as an
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