Extended Temperature 82439TX (MTXC) Datasheet
35
PRELIMINARY
3.1.19.
DRAMC
DRAM CONTROL REGISTER
Address Offset:
Default Value:
Access:
57h
01h
Read/Write
This 8-bit register controls main memory DRAM operating modes and features.
Bit
Description
7:6
Hole Enable (HEN).
This field enables a memory hole in DRAM space. CPU cycles matching an
enabled hole are passed on to PCI. PCI cycles matching an enabled hole will be ignored by the
MTXC (no DEVSEL#). Note that a selected hole is not remapped.
Bits[7:6]
Hole Enabled
00
None
01
512 KB
640 KB (128 Kbytes)
10
15 MB
16 MB (1 Mbyte)
11
14 MB
16 MB (2 Mbytes)
5
Reserved.
4
Enhanced Paging Disable (EPD).
1=MTXC keeps page open until a page/row miss. When
EPD=0, the MTXC uses additional information to keep the DRAM page open when the host may
be “right back”. See DRAM section for additional information. This bit should be set to 0 for
normal operation.
3
EDO Detect Mode Enable (EDME).
1=Enables a special timing mode for BIOS to detect EDO
DRAM type on a bank-by-bank basis. Once all DRAM row banks have been tested for EDO, the
EDME bit should be set to 0. Otherwise, performance will be seriously impacted.
2:0
DRAM Refresh Rate (DRR).
The DRAM refresh rate for “FPM/EDO only” DRAM subsystem is
adjusted according to the value selected by this field. DRAM refresh is implemented using
SUSCLK.
Bits[2:0]
DRAM Refresh Rate
000
Refresh Disabled (results in the eventual loss of DRAM data)
001
15.6 μs
010
31.2 μs (for EDO/FPM only memory subsystem)
011
64.4 μs (for EDO/FPM only memory subsystem)
100
125 μs (for EDO/FPM only memory subsystem)
101
256 μs (for EDO/FPM only memory subsystem)
110
Reserved
111
Reserved
NOTES
1.
If any of the row is populated with SDRAMs, this field must be set to 15.6 μs refresh rate.
2.
Selecting refresh rate of 125 μs or 256 μs may violate the max RAS# active time DRAM
specification. It is up to the system designer to make sure this does not happen.