參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 40/102頁
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
40
PRELIMINARY
3.1.22.
DRB
DRAM ROW BOUNDARY REGISTERS
Address Offset:
Default Value:
Access:
60–65h
02h
Read/Write
The MTXC supports 6 rows of DRAM. Each row is 64-bits wide. The DRAM Row Boundary Registers define
upper and lower addresses for each DRAM row. Contents of these 8-bit registers represent the boundary
addresses in 4-Mbytes granularity.
DRB0=Total amount of memory in row 0 (in 4 Mbytes)
DRB1=Total amount of memory in row 0 + row 1 (in 4 Mbytes)
DRB2=Total amount of memory in row 0 + row 1 + row 2 (in 4 Mbytes)
DRB3=Total amount of memory in row 0 + row 1 + row 2 + row 3 (in 4 Mbytes)
DRB4=Total amount of memory in row 0 + row 1 + row 2 + row 3 + row 4 (in 4 Mbytes)
DRB5=Total amount of memory in row 0 + row 1 + row 2 + row 3 + row 4 + row 5 (in 4 Mbytes)
The DRAM array can be configured with 512-KB, 1-MB, 4-MB, or 16-MB deep by 32- or 36-bit wide SIMMs.
Each register defines an address range that will cause a particular RAS# line to be asserted (e.g., if the first
DRAM row is 8 Mbytes, accesses within the 0 to 8-Mbytes range will cause RAS0# to be asserted).
NOTE
When programming the DRB registers, the following programming consideration must be followed:
When DRB3 is written, DRB4 and DRB5 are also modified with the value written into DRB3. When
DRB4 is written, DRB5 is also modified with the value written into DRB4. To avoid data corruption in
the DRB4 and DRB5 registers, program DRB3 first, followed by DRB4 and then DRB5. If either DRB3
or DRB4 are written, this sequence should be followed.
Bit
Description
7
Reserved.
6:0
Row Boundary Address
.
This 7-bit value is compared against the address lines A[28:22] to
determine the upper address limit of a particular row (i.e., DRB minus previous DRB=row size).
Row Boundary Address
These 8 bit values represent the upper address limits of the 6 rows (i.e., this row minus previous row=row
size). Unpopulated rows have a value equal to the previous row (row size=0). DRB5 reflects the maximum
amount of DRAM in the system. The top of memory is determined by the value written into DRB5. If DRB5 is
greater than 256 Mbytes, then 256 Mbytes of DRAM are available. BIOS must make sure that the DRB
registers do not reflect more than 256M of Main memory.
As an example of a general purpose configuration where 3 physical rows are configured for either single-
sided or double-sided SIMMs, the memory array would be configured like the one shown in Figure 3. In this
configuration, the MTXC drives two RAS# signals directly to the SIMM rows. If single-sided SIMMs are
populated, the even RAS# signal is used and the odd RAS# is not connected. If double-sided SIMMs are
used, both RAS# signals are used.
相關(guān)PDF資料
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