參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 59/102頁(yè)
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
59
PRELIMINARY
4.3.3.
DRAM ADDRESS TRANSLATION
The multiplexed row/column address to the DRAM memory array is provided by the MA[11:0] signals
(MA[13:0] for SDRAM 64-Mbit support). The MA bits are derived from the host or PCI address bus as defined
by the Table 14. The MTXC supports a 2K byte page size only. The MA lines are translated from the address
lines A[26:3] for all memory accesses.
Table 14. MTXC DRAM Address Map Summary
ADDR
MA13
MA12/
BA1
MA11/
BA0
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
Row
A24
A23
A11
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Col
A23
A26/
A11
A11/
A25
“V”
A11/
A24/
A26
A11/
A22/
A23/
A25
A10
A9
A8
A7
A6
A5
A4
A3
NOTES:
1.
V=Valid level (either 0 or 1) used for SDRAMs. It is 1 during the initialization sequence. It is 0 during
normal mode of operation.
2.
BA0 and BA1 are the muxed bank selects for SDRAM. Bank select BA1 is required for 64-Mbit SDRAM
support.
4.3.4.
DRAM PAGING
If DRAMC[bit 4]=1, the MTXC keeps the page open until a page or row miss occurs. If DRAMC[bit 4]=0
(default), the DRAM page is kept open when:
CPU host bus is non-idle, or
PCI interface owns the bus.
4.3.5.
DRAM TYPES
4.3.5.1.
FPM Mode
The MTXC, as a default, supports the standard fast page mode (FPM) DRAM.
4.3.5.2.
EDO Mode
Extended Data Out (or Hyper Page Mode) DRAM is designed to improve the DRAM read performance. EDO
DRAM holds the memory data valid until the next CAS# falling edge. Compared to standard page mode
DRAM which tri-states the memory data when CAS# negates to precharge. With EDO, the CAS# precharge
overlaps the memory data valid time. This allows CAS# to negate earlier while still satisfying the memory
data valid window time.
4.3.5.3.
SDRAM Mode
Synchronous DRAM (SDRAM) implements a fully synchronous interface as compared to a conventional
DRAM whose timing delays are related to the rising and falling edges of the RAS#, CAS#, and WE# input
signals. The 430TX supports all of the features and timings as shown in the “SDRAM PC” specification. The
objective of the
SDRAM
PC Specification is to enable low cost and easily manufacturable SDRAMs for the
main stream volume desktop and Mobile PC’s. There are three grade parts defined for the 430TX. All of the
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