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| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 30/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
30
PRELIMINARY
Bit
Description
5:4
L2 SRAM Type (L2SRAMT)
.
This field reflects the inverted signal level on the A[29:28] pins at
the rising edge of the RESET signal. The RESET values can be overwritten with subsequent
writes to the CC Register. The options are:
Bits[5:4]
SRAM Type
00
01
10
11
Pipelined Burst SRAM
Reserved
Reserved
Two banks of Pipelined Burst
NOTE
When 512k, Two Banks of Pipelined Burst mode is selected (SCS = 10 and L2SRAMT = 11),
NA# will be delayed by one HCLK during burst reads from L2 to ensure that the active bank is
not de-selected too early by pipelining a cycle to the opposite bank.
Pipelined Burst SRAM (bits 5:4 = 00) also applies to a 512k L2 size when two 64kx32 SRAM
devices are used.
3
NA Disable (NAD).
1=Disable. 0=Enable.
When disabled, MTXC never asserts the NA# pin.
When enabled, NA# assertion is dependent on the cache type and size selected (via SRAMT,
SCS). Note that NAD must be set to 1 if the NA# pin of the MTXC is not connected to the
processor. This bit should be set to 0 for normal operation in systems that connect NA# to the
processor.
2
Reserved.
1
Secondary Cache Force Miss or Invalidate (SCFMI)
.
When set to a 1, the L2 hit/miss detection
is disabled, and all tag lookups result in a miss. If the L2 is enabled, then the cycle is processed
as a miss (as described in Chapter 4.2). If the L2 is populated but disabled (FLCE=0), then when
SCFMI is set to a 1, any CPU read cycle will invalidate the selected tag entry. When SCFMI is set
to a 0, normal L2 cache hit/miss detection and cycle processing occurs.
Software can flush the cache (cause all modified lines to be written back to DRAM) by setting
SCFMI to a 1 with the L2 enabled (non-zero SCS, FLCE=1), and reading all L2 cache tag address
locations. See FLCE bit description for FLCE/SCFMI interaction.
0
First Level Cache Enable (FLCE)
.
1=Enable. 0=Disable. When FLCE=1, the MTXC responds to
CPU cycles with KEN# asserted for cacheable memory cycles. When FLCE=0, KEN# is always
negated. This prevents new cache line fills to either the first level or second level cache.
The FLCE/SCFMI interaction is summarized below. Note that “Normal L2 operation” is further
dependent on the SCS field programming.
FLCE
0
0
1
1
SCFMI
0
1
0
1
L2 Result
L2 disabled
L2 disabled, MTXC tag invalidate on reads
Normal L2 operation (dependent on SCS)
L2 enabled, MTXC miss forced on reads/writes (Note that writes to the
cache are also forced as misses, making it possible to create incoherent
DRAM/L2 data.)
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