參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 56/102頁
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
56
PRELIMINARY
upgrade path by the end user; the size and type of DRAM that can be implemented in the 5th row is
limited (see the bullets below).
The total memory supported is 256 MB, even though it is possible to populate the six rows with more than
256 MB. This limit must be ensured by the system BIOS.
EDO/FPM only configuration Requirements
If more than four rows of x4 DRAM devices + one row of x8 DRAM devices of memory is supported, it is
recommended that all six rows be buffered. MA and MWE# enable signals should be buffered. In a
system that only supports x8 or x16 devices (i.e., x4 devices not supported), six rows of memory can be
supported without buffering.
Maximum load supported without buffers: Four rows of x4 DRAM devices + one row of x8 DRAM devices.
A second pair or MA0 and MA1 signals are provided by muxing CKE with MAA0 and CKEB with MAA1.
In a desktop system, it is required that the second pair of MA lines be used to support 5-2-2-2 EDO
performance in more than two rows of memory. The second pair of MA lines are not required in a mobile
system, assuming x4 devices are not used. The MA functionality is selected via DRAMC[bit 2] (67h).
SDRAM only configuration Requirements
Maximum rows supported; Five rows of x8 devices.
SDRAM/EDO/FPM mixing configuration Requirements
If SDRAM and EDO/FPM are mixed in a system, the configuration is limited to a maximum of four rows
(two rows of x4 EDO/FPM and two rows of x8 or x16 SDRAM). If only x8 or x16 EDO/FPM and SDRAM
devices are used (i.e., not x4’s), five rows can be supported.
SDRAMs can be mixed with EDO/FPM on a row by row basis (e.g., row 0 can be populated with
SDRAMs while row 3 is populated with EDO/FPM).
A second pair or MA0 and MA1 signals are provided by muxing CKE with MAA0 and CKEB with MAA1.
In a desktop system, it is required that the second pair of MA lines be used to support 5-2-2-2 EDO
performance in more than two rows of memory. The second pair of MA lines are not required in a mobile
system, assuming x4 devices are not used. The MA functionality is selected via DRAMC[bit 2] (67h).
Table 12 provides a summary of the characteristics of memory configurations supported by the MTXC.
Minimum values listed are obtained with single-sided SIMMs or DIMMs. Maximum values are obtained with
double-sided SIMMs or DIMMs. Note that, for a 64-bit wide memory array, a minimum of two 32-bit wide
DRAM SIMMs are required in any specific row. The minimum values used are also the smallest upgradeable
memory size. Please note that EDO/FPM can also come on x64 DIMM modules.
相關(guān)PDF資料
PDF描述
FW82815 Controller Miscellaneous - Datasheet Reference
FWA-25A10F Fuse
FWA-30A10F Fuse
FWA-35A21F Fuse
FWA-40A21F Fuse
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FW82439TX S L28T 制造商:Intel 功能描述:System Controller 324-Pin BGA
FW82439TX S L3BT 制造商:Intel 功能描述:System Controller
FW82439TX S L28T 制造商:Intel 功能描述:
FW82439TX S L3BT 制造商:Intel 功能描述:System Controller
FW82439TXSL28T 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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