參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 38/102頁(yè)
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
38
PRELIMINARY
Each PAM Register controls two regions, typically 16 Kbytes in size. Each of these regions has a 4-bit field.
The four bits that control each region have the same encoding and are defined in Table 6.
PCI master access to DRAM space is also controlled by the PAM Registers. If the PAM programming
indicates a region is writeable, then PCI master writes will be accepted (DEVSEL# generated). If the PAM
programming indicates a region is readable, PCI master reads will be accepted. If a PCI write to a non-
writeable DRAM region, or a PCI read to a non-readable DRAM region is seen, the MTXC will not accept the
cycle (DEVSEL# will not be asserted). PCI master accesses to enable memory hole regions will not be
accepted.
Table 6. Attribute Bit Assignment
Bits [7, 3]
Reserved
Bits [6, 2]
Cache Enable
Bits [5, 1]
Write Enable
Bits [4, 0]
Read Enable
Description
x
x
0
0
DRAM disabled, accesses directed
to PCI
x
0
0
1
read only, DRAM write protected,
non-cacheable
x
1
0
1
read only, DRAM write protected, L1
cacheable for code accesses only
x
0
1
0
write only
x
0
1
1
read/write, non-cacheable
x
1
1
1
read/write, cacheable
As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process
the BIOS can be shadowed in main memory to increase the system performance. When a BIOS is shadowed
in main memory, it should be copied to the same address location. To shadow the BIOS, the attributes for
that address range should be set to write only. The BIOS is shadowed by first doing a read of that address.
This read is forwarded to the expansion bus. The CPU then does a write of the same address, which is
directed to main memory. After the BIOS is shadowed, the attributes for that memory area are set to read
only so that all writes are forwarded to the expansion bus.
Table 7. PAM Register and Associated Memory Segments
PAM Reg.
Attribute Bits
Memory Segment
Comments
Offset
PAM0[3:0]
Reserved
59h
PAM0[7:4]
R
CE
WE
RE
0F0000h – 0FFFFFh
BIOS Area
59h
PAM1[3:0]
R
CE
WE
RE
0C0000h – 0C3FFFh
ISA Add-on BIOS
5Ah
PAM1[7:4]
R
CE
WE
RE
0C4000h – 0C7FFFh
ISA Add-on BIOS
5Ah
PAM2[3:0]
R
CE
WE
RE
0C8000h – 0CBFFFh
ISA Add-on BIOS
5Bh
PAM2[7:4]
R
CE
WE
RE
0CC000h – 0CFFFFh
ISA Add-on BIOS
5Bh
PAM3[3:0]
R
CE
WE
RE
0D0000h – 0D3FFFh
ISA Add-on BIOS
5Ch
PAM3[7:4]
R
CE
WE
RE
0D4000h – 0D7FFFh
ISA Add-on BIOS
5Ch
PAM4[3:0]
R
CE
WE
RE
0D8000h – 0DBFFFh
ISA Add-on BIOS
5Dh
PAM4[7:4]
R
CE
WE
RE
0DC000h – 0DFFFFh
ISA Add-on BIOS
5Dh
PAM5[3:0]
R
CE
WE
RE
0E0000h – 0E3FFFh
BIOS Extension
5Eh
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