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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 45/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
45
PRELIMINARY
3.1.27.
SMRAMC
SYSTEM MANAGEMENT RAM CONTROL REGISTER
Address Offset:
Default Value:
Access:
72h
02h
Read/Write
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated.
MTXC supports two types of SMRAM memory: Compatible and Extended. The Open, Close, and Lock bits
function only when G_SMRAME bit is set to a 1. Also, the OPEN bit be reset before the LOCK bit is set.
Bit
Description
7
Reserved.
6
SMM Space Open (D_OPEN)
.
When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made
visible even when SMIACT# is negated. This is intended to help BIOS initialize SMM space.
Software should ensure that D_OPEN=1 is mutually exclusive with D_CLS=1. When D_LCK is
set to a 1, D_OPEN is reset to 0 and becomes read only.
5
SMM Space Closed (D_CLS)
.
When D_CLS=1, SMM space DRAM is not accessible to data
references, even if SMIACT# is asserted. Code references may still access SMM space DRAM.
This will allow SMM software to reference “through” SMM space to update the display, even when
SMM space is mapped over the VGA range. Software should ensure that D_OPEN=1 is mutually
exclusive with D_CLS=1.
4
SMM Space Locked (D_LCK)
.
When D_LCK is set to 1, D_OPEN is reset to 0 and both D_LCK
and D_OPEN become read only. D_LCK can be set to 1 via a normal configuration space write
but can only be cleared by a power-on reset. The combination of D_LCK and D_OPEN provide
convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and
then use D_LCK to “l(fā)ock down” SMM space in the future so that no application software (or BIOS
itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN
function.
3
Global SMRAM Enable (G_SMRAME)
. If set to a 1, then Compatible SMRAM functions is
enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADS# with
SMIACT#). To enable Extended SMRAM function this bit has be set to 1. Refer to the section on
SMM for more details.
2:0
Compatible SMM Space Base Segment (C_BASE_SEG).
This field programs the location of
SMM space. SMM DRAM is not remapped. It is simply “made visible” if the conditions are right to
access SMM space; otherwise, the access is forwarded to PCI. C_BASE_SEG=010 selects the
SMM space as A0000–BFFFFh. All other values are reserved. PCI initiators are not allowed to
access to SMM space. These bits are hardwired to 010.
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