參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 63/102頁(yè)
文件大小： 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
63
PRELIMINARY
Table 18 lists the performance summary for SDRAM. The CL= 3 column represents a CAS latency of 3 part
with a RAS to CAS (Trcd) of two clocks. The CL=2 column represents a CAS latency of two part. The
performance numbers in Table 18 assume each row is populated with a maximum of eight, x8 devices=40
SDRAM devices.
The SLD bit (page hit, row miss, and page miss) is used to control the leadoff for read cycles. This bit
removes one clock from the leadoff, when enabled.
Table 18. SDRAM Performance Summary
Processor Cycle Type
60/66 MHz
CL=3
Five Rows (Max)
60/66 MHz
CL=2
Five Rows (Max)
Burst Read Page Hit
7-1-1-1
6-1-1-1
Read row Miss
1
9-1-1-1
8-1-1-1
Read Page Miss
12-1-1-1
11-1-1-1
Back-to-Back Burst Reads Page Hit
7-1-1-1 2-1-1-1
6-1-1-1 2-1-1-1
Write Page Hit
2,3
3
3
Write Row Miss
2,3
6
5
Write Page Miss
2,3
9
8
Posted Write
2,3
3-1-1-1
3-1-1-1
Write retire rate from Posted Write Buffer
-1-1-1
-1-1-1
Reg 54h, Bit 5 (RCO)
5
1
0
Reg 54h, Bit 4 (CL)
0
1
Reg 54h, Bit 3 (RT)
0
1
Reg 56h, Bit 4 (SLD)
4
0
0
NOTES:
1.
The row miss cycle assumes that the new page is closed from the prior cycle.
2.
This cycle timing assumes the write buffer(DWB) is empty.
3.
Write data is always posted as 3-1-1-1 (ADS# to BRDY#), if write buffers is available.
4.
This bit (SLD) must be set to a 1 (speculative leadoff disable) in systems with cache and to 0 in systems
without cache.
5.
For a CL=3 part that can not meet a RAS to CAS timing (Trcd) of two HCLKs, RCO can be set to 0. This
will add an HCLK to the leadoff cycle for Row miss and Page miss cycles.
相關(guān)PDF資料
PDF描述
FW82815 Controller Miscellaneous - Datasheet Reference
FWA-25A10F Fuse
FWA-30A10F Fuse
FWA-35A21F Fuse
FWA-40A21F Fuse
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