參數(shù)資料
型號： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 22/102頁
文件大小： 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
22
PRELIMINARY
3.1.3.
CONFDATA
CONFIGURATION DATA REGISTER
I/O Address:
Default Value:
Access:
0CFCh
00000000h
Read/Write
CONFDATA is a 32-bit read/write window into configuration space. The portion of configuration space that is
referenced by CONFDATA is determined by the contents of CONFADD.
Bit
Descriptions
31:0
Configuration Data Window (CDW).
If bit 31 of CONFADD is 1, any I/O reference that falls in
the CONFDATA I/O space is mapped to configuration space using the contents of CONFADD.
PCI Configuration Space Mapped Registers
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to 256 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space
Configuration Read
and
Configuration Write
. While memory and I/O spaces are supported by the Pentium
microprocessor, configuration space is not supported. The PCI specification defines two mechanisms to
access configuration space, Mechanism #1 and Mechanism #2. The MTXC supports only Mechanism #1.
The bus cycles used to access MTXC internal configuration registers are described later in the PCI cycle
timings section.
The configuration access mechanism makes use of the CONFADD Register and CONFDATA Register. To
reference a configuration register, a DWord I/O write cycle is used to place a value into CONFADD that
specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration
register of the device function being accessed. CONFADD[31] must be 1 to enable a configuration cycle.
CONFDATA then becomes a window onto four bytes of configuration space specified by the contents of
CONFADD. Any read or write to CONFDATA will result in the MTXC translating CONFADD into a PCI
configuration cycle.
Type 0 Access
If the Bus Number field of CONFADD is 0 a Type 0 Configuration cycle is performed on PCI. CONFADD[10:2]
is mapped directly to AD[10:2]. The Device Number field of CONFADD is decoded onto AD[31:11]. The
MTXC is Device #0 and does not pass its configuration cycles to PCI so AD11 will never be asserted. Device
#1 will assert AD12, Device #2 will assert AD13, and so forth up to Device #20 which will assert AD31. Only
one AD line is asserted at a time. All device numbers higher than 20 cause a type 0 configuration access with
no IDSEL asserted, which will result in a Master Abort.
Type 1 Access
If the Bus Number field of CONFADD is non-zero a Type 1 Configuration cycle is performed on PCI.
CONFADD[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to 01 to indicate a Type 1 Configuration
cycle. All other lines are driven to 0.
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