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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 26/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
26
PRELIMINARY
Bit
Description
3
Special Cycle Enable (SCE)
.
(Not implemented)
This bit is hardwired to 0, as the MTXC does
not respond to PCI special cycles.
2
Bus Master Enable (BME)
.
(Not implemented)
This bit is hardwired to 1. The MTXC does not
support disabling of its bus master capability on the PCI Bus.
1
Memory Access Enable (MAE)
.
When MAE=1, the MTXC permits PCI masters to access main
memory if the PCI address selects enabled DRAM space. When MAE=0, the MTXC does not
respond to main memory accesses.
0
I/O Access Enable (IOAE)
.
(Not implemented)
The MTXC does not respond to PCI I/O cycles.
This bit is hardwired to 0.
3.1.7.
PCISTS
PCI STATUS REGISTER
Address Offset:
Default Value:
Access:
06–07h
0200h
Read Only, Read/Write Clear
PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target abort.
PCISTS also indicates the DEVSEL# timing that has been set by the MTXC hardware.
Bit
Description
15
Detected Parity Error (DPE).
This bit is hardwired to 0, as PCI received parity checking is not
implemented by the MTXC.
14
Signaled System Error (SSE).
This bit is hardwired to 0 as MTXC does not support SERR#.
13
Received Master Abort Status (RMAS).
When the MTXC terminates a Host-to-PCI transaction
(MTXC is a PCI master) with an unexpected master abort, this bit is set to 1. Note that master
abort is the normal and expected termination of PCI special cycles. Software resets this bit to 0
by writing a 1 to it.
12
Received Target Abort Status (RTAS).
When a MTXC-initiated PCI transaction is terminated
with a target abort, RTAS is set to 1. Software resets RTAS to 0 by writing a 1 to it.
11
Signaled Target Abort Status (STAS).
This bit is hardwired to 0, as the MTXC never terminates
a PCI cycle with a target abort.
10:9
DEVSEL# Timing (DEVT)
.
This 2-bit field indicates the timing of the DEVSEL# signal when the
MTXC responds as a target, and is hardwired to the value 01b (medium) to indicate the slowest
time that DEVSEL# is generated.
8
Data Parity Detected (DPD)
.
This bit is hardwired to 0, as PERR# is not implemented.
7
Fast Back-to-Back (FB2B).
This bit is hardwired to 0, as fast back to back cycle generation is
not implemented.
6
User Defined Format (UDF).
This bit is hardwired to 0. This is because the MTXC does not
contain any configurations that depend on the environment, such as network frequencies.
5
66-MHz PCI Capable (66C).
This bit is hardwired to 0. The MTXC does not interface to 66-MHz
PCI.
4:0
Reserved
.
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