參數(shù)資料
型號： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 51/102頁
文件大小： 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
51
PRELIMINARY
4.2.1.
CLOCK LATENCIES
Table 11 lists the latencies for various processor transfers to and from the second level cache.
Table 11. Second Level Cache Latencies with Pipelined Burst SRAM
Cycle Type
HCLK Count
Burst Read
3-1-1-1
Burst Write (write back)
3-1-1-1
Single Read
3
Single Write
3
Pipelined Back-to-Back Burst Reads
3-1-1-1,1-1-1-1 (note 1)
NOTES:
1.
The back to back cycles do not account for CPU idle clocks between cycles.
4.2.2.
SNOOP CYCLES
The snoop (or inquire) cycle is used to probe the first level and second level caches when a PCI master
attempts to access main memory. This is done in order to maintain coherency between the first and second
level caches and main memory.
To maintain optimum PCI bandwidth to DRAM, the MTXC utilizes a snoop ahead algorithm. Once the snoop
for the first cache line of a transfer has completed, the MTXC automatically snoops the next sequential cache
line. This algorithm enables the MTXC to continue burst transfers across cache line boundaries.
Reads
Snoop cycles are performed by driving the PCI master address onto the host address bus and asserting
EADS#. The processor then performs a tag lookup to determine whether the addressed memory is in the first
level cache. If the snoop hit is to a Modified Line in the first level cache (HITM# asserted), then the line in the
first level cache is posted to the DRAM Posted Write buffers. The line in the second level cache (if it exists) is
invalidated. The line in the first level cache is not invalidated if the INV pin on the CPU is tied to the KEN#
signal from the MTXC. KEN#/INV will be driven low by the MTXC with EADS# assertion during PCI master
read cycles.
At the same time as the first level snoop cycle, the MTXC performs a tag lookup to determine whether the
addressed memory is in the second level cache. A hit to a modified line in the second level cache also results
in a writeback to DRAM posted write buffers if HITM# is not asserted. The PCI data is serviced from the
DRAM after the line has been retired to DRAM.
Writes
PCI Master write cycles never result in a write directly into the second level cache. A snoop hit to a modified
line in either the first or second caches results in a writeback of that line to main memory. If both the first and
second level caches have modified lines, then the line is written back from the first level cache. In all cases
lines in the first and second level caches are invalidated and the PCI write to main memory occurs after the
writeback completes. A PCI master write snoop hit to an unmodified line in either the first or second level
caches results in the line being invalidated. KEN#/INV will be driven high by the MTXC with EADS# assertion
during PCI master write cycles.
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