參數(shù)資料
型號： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 29/102頁
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
29
PRELIMINARY
3.1.14.
PCON
PCI CONTROL REGISTER
Address Offset:
Default Value:
Access:
50h
00h
Read/Write
The PCON Register enables and disables features related to the PCI bus that are not already covered in the
required PCI space.
Bit
Description
7:4
Reserved.
3
PCI Concurrency Enable (PCE).
1=CPU can access DRAM and L2 while a non-PIIX4 PCI
master is targeting Peer PCI devices. 0 (default)=CPU is held off of the bus during all PCI master
cycles. This bit should be set to 1 by BIOS during normal operation
.
2:0
Reserved.
3.1.15.
CC
CACHE CONTROL REGISTER
Address Offset:
Default Value:
Access:
52h
SSSS0010 (S=Strapping option)
Read/Write
This 8-bit register defines the secondary cache operations. The CC register enables and disables the second
level cache, adjusts cache size, selects the cache write policy, selects the caching policy when CACHE# is
negated on reads, informs the MTXC how the SRAMs are connected, and defines the cache SRAM type.
After a hard reset, CC[7:4] reflect the signal levels on the Host address lines A[31:28].
Bit
Description
7:6
Secondary Cache Size (SCS)
.
This field reflects the inverted signal level on the A[31:30] pins at
the rising edge of the RESET signal. The options are:
Bits[7:6]
Secondary Cache Size
00
01
10
11
Cache not populated
256 Kbytes
512 Kbytes
Reserved
The RESET values can be overwritten with subsequent writes to the CC Register.
NOTE
1.
2. When bits[7:6]
≠
00, the FLCE bit must also be set to 1 (L2 cache cannot be enabled
unless the L1 cache is also enabled).
When bits[7:6]=00, the secondary cache is disabled.
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參數(shù)描述
FW82439TX S L28T 制造商:Intel 功能描述:System Controller 324-Pin BGA
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