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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 15/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
15
PRELIMINARY
2.1.5.
TEST AND CLOCK
Name
Type
Description
TEST#
I
3.3/5V
Test In.
NAND tree mode is activated by driving this pin low. The test mode selected
depends on the state of REQ[3:0]#. This pin should be pulled high with an external
pull-up during normal operation.
HCLKIN
I
3.3/2.5
V
Host Clock In.
This pin receives a buffered host clock. This clock is used by all of the
MTXC logic that is in the Host clock domain.
PCLKIN
I
3.3/5V
PCI Clock In.
This pin receives a buffered divide-by-2 host clock. This clock is used
by all of the MTXC logic that is in the PCI clock domain.
2.1.6.
POWER MANAGEMENT
Name
Type
Description
SUSCLK
I
3.3V
Suspend Clock.
The signal is a 32 KHz input for DRAM refresh circuitry and
clocking events in suspend state. The DRAM refresh during suspend and
non-suspend states is performed based on this clock. This signal has an internal
pull-down resistor.
SUSSTAT1#
I
3.3V
Suspend Status.
SUSSTAT1# indicates MTXC’s power plane status during
suspend mode. SUSSTAT1#, along with SUSCLK and RST#, define the suspend
protocol between MTXC and PIIX4. This signal has an internal pull-up resistor.
2.1.7.
POWER AND GROUND PINS
Name
Type
Description
V
CC
3.3V
Main voltage supply.
These pins are the primary voltage supply for the MTXC core
and I/O periphery and must be connected to 3.3V.
V
CC
(CPU)
3.3V
or
2.5V
CPU Interface Voltage Supply.
These pins are the primary voltage supply for the
MTXC Host periphery and must be connected to either 2.5V or 3.3V, depending on
the voltage level of the CPU interface. Refer to the Power sequencing requirements
section for additional details.
V
CC
(SUS)
3.3V
Suspend Well Voltage Supply.
These pins are the primary voltage supply for the
MTXC suspend logic and I/O. If suspend to RAM is supported, these pins should be
on an isolated power plane; otherwise, they can be connected to the same 3.3V
source used for the V
CC
pins.
V
CC
5REF
3.3V
or 5V
Voltage Reference.
This pin is tied to 5V through a small external power sequencing
circuit, if MTXC signals are required to be 5V Tolerant. In a non 5V tolerant system
(i.e. 3.3V only system), this signal can be tied directly to V
CC
. Refer to the Power
sequencing requirements section for additional details.
V
SS
0V
Ground.
These pins are the ground for the MTXC.
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