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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 48/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
48
PRELIMINARY
4.0.
FUNCTIONAL DESCRIPTION
4.1.
Host Interface
The Host Interface of the MTXC is designed to support the Pentium microprocessor. The host interface of the
MTXC supports 60-, and 66-MHz bus speeds. The Intel 430TX PCIset supports the Pentium microprocessor
with a full 64-bit data bus, 32-bit address bus, and associated internal writeback cache logic. Host bus
addresses are decoded by the MTXC for accesses to main memory, PCI memory, and PCI I/O. The MTXC
also supports the pipelined addressing capability of the Pentium microprocessor.
4.2.
Secondary Cache Interface
The MTXC integrates a high performance writeback second level cache controller using internal/external tags
and provides a full first level and second level cache coherency mechanism. The second level cache is direct
mapped, nonsectored, and supports a writeback, no write allocate (lines are not allocated on write misses)
write policy.
The second level cache can be configured to support either a 256-KB or 512-KB cache using synchronous
pipelined burst SRAM or DRAM Cache. One additional PCIset signal (KRQAK) is required to support DRAM
Cache. 64-Mbytes cacheability coverage is obtained with 8Kx8 standard SRAM to store the tags for 256-KB
configuration. For the 512-KB configurations, a 16Kx8 standard SRAM is used to store the tags and the valid
bits for 64-MB cacheability.
A second level cache line is 32-bytes wide. In the 256-KB configurations, the second level cache contains
8K lines, while the 512-KB configurations contain 16K lines. Valid and modified status bits are kept on a per
line basis. Cacheability of the entire memory space in first level cache is supported, while only the lower 64
MB of main memory is cacheable in the second level cache. Table 9 shows the tag sizes needed to support
different sizes of cacheability. Only main memory controlled by the MTXC DRAM interface is cached. PCI
memory is not cached.
Table 9. Cacheability
Cache Size
Tag Size
Cacheability
256 Kbytes
8K by 8 bits
64 Mbytes
512 Kbytes
16K by 8 bits (including valid bit)
64 Mbytes
The following table shows the different standard SRAM access time requirements for different host clock
frequencies.
Table 10. SRAM Access Time Requirements
Host Clock Frequency (MHz)
Pipelined Burst Clock-to-Output
Access Time (ns)
Tag RAM Cycle Time (ns)
60
10
15
66
8.5
15
相關PDF資料 |
PDF描述 |
|---|---|
| FW82815 | Controller Miscellaneous - Datasheet Reference |
| FWA-25A10F | Fuse |
| FWA-30A10F | Fuse |
| FWA-35A21F | Fuse |
| FWA-40A21F | Fuse |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FW82439TX S L28T | 制造商:Intel 功能描述:System Controller 324-Pin BGA |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TX S L28T | 制造商:Intel 功能描述: |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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